Datasheet

662
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
35.4 Application Block Diagram
Figure 35-2. Application Block Diagram: Single Master/Multiple Slave Implementation
35.5 Signal Description
35.6 Product Dependencies
35.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must
first program the PIO controllers to assign the SPI pins to their peripheral functions.
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK
MISO
MOSI
NSS
Slave 0
SPCK
MISO
MOSI
NSS
Slave 1
SPCK
MISO
MOSI
NSS
Slave 2
NC
NPCS3
Table 35-1. Signal Description
Pin Name Pin Description
Type
Master Slave
MISO Master In Slave Out Input Output
MOSI Master Out Slave In Output Input
SPCK Serial Clock Output Input
NPCS1-NPCS3 Peripheral Chip Selects Output Unused
NPCS0/NSS Peripheral Chip Select/Slave Select Output Input
Table 35-2. I/O Lines
Instance Signal I/O Line Peripheral
SPI0 SPI0_MISO PA11 A
SPI0 SPI0_MOSI PA12 A