Datasheet

648
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
1 = The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded. Cleared by reading in the
HSMCI_SR register.
• CSTOE: Completion Signal Time-out Error
0 = No error.
1 = The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been exceeded. Cleared by reading
in the HSMCI_SR register. Cleared by reading in the HSMCI_SR register.
• BLKOVRE: DMA Block Overrun Error
0 = No error.
1 = A new block of data is received and the DMA controller has not started to move the current pending block, a block overrun is
raised. Cleared by reading in the HSMCI_SR register.
• DMADONE: DMA Transfer done
0 = DMA buffer transfer has not completed since the last read of the HSMCI_SR register.
1 = DMA buffer transfer has completed.
• FIFOEMPTY: FIFO empty flag
0 = FIFO contains at least one byte.
1 = FIFO is empty.
• XFRDONE: Transfer Done flag
0 = A transfer is in progress.
1 = Command Register is ready to operate and the data bus is in the idle state.
• ACKRCV: Boot Operation Acknowledge Received
0 = No Boot acknowledge received since the last read of the status register.
1 = A Boot acknowledge signal has been received. Cleared by reading the HSMCI_SR register.
• ACKRCVE: Boot Operation Acknowledge Error
0 = No error
1 = Corrupted Boot Acknowledge signal received.
• OVRE: Overrun
0 = No error.
1 = At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command.
When
FERRCTRL in HSMCI_CFG is set to 1, OVRE becomes reset after read.
• UNRE: Underrun
0 = No error.
1 = At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer com-
mand or when setting
FERRCTRL in HSMCI_CFG to 1.
When FERRCTRL in HSMCI_CFG is set to 1, UNRE becomes reset after read.