Datasheet

642
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
34.14.8 HSMCI Completion Signal Timeout Register
Name: HSMCI_CSTOR
Address: 0xF000801C (0), 0xF000C01C (1)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “H SMCI Write Protect Mode Register” on page 657.
• CSTOCYC: Completion Signal Timeout Cycle Number
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. Its
value is calculated by (CSTOCYC x Multiplier).
• CSTOMUL: Completion Signal Timeout Multiplier
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. Its
value is calculated by (CSTOCYC x Multiplier).
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the data transfer
and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If a non-DATA
ATA command is issued, the HSMCI starts waiting immediately after the end of the response until the completion signal.
Multiplier is defined by CSTOMUL as shown in the following table:
If the data time-out set by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error flag (CSTOE) in
the HSMCI Status Register (HSMCI_SR) rises.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– CSTOMUL CSTOCYC
Value Name Description
0 1 CSTOCYC x 1
1 16 CSTOCYC x 16
2 128 CSTOCYC x 128
3 256 CSTOCYC x 256
4 1024 CSTOCYC x 1024
5 4096 CSTOCYC x 4096
6 65536 CSTOCYC x 65536
7 1048576 CSTOCYC x 1048576