Datasheet

598
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
32.7.25 UDPHS DMA Channel Status Register
Name: UDPHS_DMASTATUSx [x = 0..5]
Address: 0xF803C30C [0], 0xF803C31C [1], 0xF803C32C [2], 0xF803C33C [3], 0xF803C34C [4], 0xF803C35C [5]
Access: Read-write
Note: Channel 0 is not used.
• CHANN_ENB: Channel Enable Status
0 = If cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx regis-
ter LDNXT_DSC bit is set.
When any transfer is ended either due to an elapsed byte count or a UDPHS device initiated transfer end, this bit is automatically
reset.
1 = If set, the DMA channel is currently enabled and transfers data upon request.
This bit is normally set or cleared by writing into the UDPHS_DMACONTROLx register CHANN_ENB bit field either by software
or descriptor loading.
If a channel request is currently serviced when the UDPHS_DMACONTROLx register CHANN_ENB bit is cleared, the DMA FIFO
buffer is drained until it is empty, then this status bit is cleared.
• CHANN_ACT: Channel Active Status
0 = The DMA channel is no longer trying to source the packet data.
When a packet transfer is ended this bit is automatically reset.
1 = The DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.
When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor load (if
any) and potentially until UDPHS packet transfer completion, if allowed by the new descriptor.
• END_TR_ST: End of Channel Transfer Status
0 = Cleared automatically when read by software.
1 = Set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer.
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
• END_BF_ST: End of Channel Buffer Status
0 = Cleared automatically when read by software.
1 = Set by hardware when the BUFF_COUNT downcount reach zero.
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
31 30 29 28 27 26 25 24
BUFF_COUNT
23 22 21 20 19 18 17 16
BUFF_COUNT
15 14 13 12 11 10 9 8
––––––––
76543210
– DESC_LDST END_BF_ST END_TR_ST – – CHANN_ACT CHANN_ENB