Datasheet

550
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Figure 32-18.Stall Handshake Data IN Transfer
32.6.11 Speed Identification
The high speed reset is managed by the hardware.
At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset.
At the end of the reset process (full or high), the ENDRESET interrupt is generated.
Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of the device.
32.6.12 USB V2.0 High Speed Global Interrupt
Interrupts are defined in Section 32.7.3 ”UDPHS Interrupt Enable Register” (UDPHS_IEN) and in Section 32.7.4
”UDPHS Interrupt Status Register” (UDPHS_INTSTA).
32.6.13 Endpoint Interrupts
Interrupts are enabled in UDPHS_IEN (see Section 32.7.3 ”UDPHS Interrupt Enable Register”) and individually masked
in UDPHS_EPTCTLENBx (see Section 32.7.9 ”UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt
Endpoints)”).
Token IN Stall PID
USB Bus
Packets
Cleared by Firmware
Set by Firmware
FRCESTALL
STALL_SNT
Set by Hardware
Cleared by Firmware
Interrupt Pending
Table 32-5. Endpoint Interrupt Source Masks
SHRT_PCKT Short Packet Interrupt
BUSY_BANK Busy Bank Interrupt
NAK_OUT NAKOUT Interrupt
NAK_IN/ERR_FLUSH NAKIN/Error Flush Interrupt
STALL_SNT/ERR_CRC_NTR
Stall Sent/CRC error/Number of Transaction
Error Interrupt
RX_SETUP/ERR_FL_ISO Received SETUP/Error Flow Interrupt
TXRDY_TRER TX Packet Read/Transaction Error Interrupt
TX_COMPLT Transmitted IN Data Complete Interrupt
RXRDY_TXKL Received OUT Data Interrupt
ERR_OVFLW Overflow Error Interrupt
MDATA_RX MDATA Interrupt
DATAX_RX DATAx Interrupt