Datasheet

52
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
11.3 Chip Setup
At boot start-up, the processor clock (PCK) and the master clock (MCK) source is the 12 MHz Fast RC Oscillator.
Initialization follows the steps described below:
1. Stack setup for ARM supervisor mode.
2. Main Oscillator Detection: the Main Clock is switched to the 32 kHz RC oscillator to allow external clock fre-
quency to be measured. Then the Main Oscillator is enabled and set in bypass mode. If the MOSCSELS bit rises,
an external clock is connected, and the next step is Main Clock Selection (3). If not, the bypass mode is cleared to
attempt external quartz detection. This detection is successful when the MOSCXTS and MOSCSELS bits rise,
else the 12 MHz Fast RC internal oscillator is used as the Main Clock.
3. Main Clock Selection: the Master Clock source is switched from the Slow Clock to the Main Oscillator without
prescaler. The PMC Status Register is polled to wait for MCK Ready. PCK and MCK are now the Main Clock.
4. C variable initialization: non zero-initialized data is initialized in the RAM (copy from ROM to RAM). Zero-initial-
ized data is set to 0 in the RAM.
5. PLLA initialization: PLLA is configured to get a PCK at 96 MHz and an MCK at 48 MHz. If an external clock or
crystal frequency running at 12 MHz is found, then the PLLA is configured to allow communication on the USB link
for the SAM-BA Monitor; else the Main Clock is switched to the internal 12 MHz Fast RC, but USB will not be
activated
.
Note that if the clock frequency is provided not at 12 MHz but between 4 and 28 MHz, it is considered by the ROM Code
as the 12 MHz clock frequency, and the PLL settings are configured accordingly.
11.4 NVM Boot
11.4.1 NVM Boot Sequence
The boot sequence on external memory devices can be controlled using the Boot Sequence Configuration Register
(BSC_CR). The 3 LSBs of the BSC_CR are available to control the sequence. See the “Boot Sequence Controller
(BSC)” section for more details.
The user can then choose to bypass some steps shown in Figure 11-2 “NVM Bootloader Sequence Diagram” according
to the BSC_CR Value.
Table 11-1. External Clock and Crystal Frequencies allowed for Boot Sequence (in MHz)
Boot Sequence ≤ 412≥ 28
Boot on External Memories Yes Yes Yes
SAM-BA Monitor through DBGU Yes Yes Yes
SAM-BA Monitor through USB No Yes No
Table 11-2. Boot Sequence Configuration Register Values
BOOT Value SPI0 NPCS0 SDCard
NAND
Flash SPI0 NPCS1 TWI EEPROM
SAM-BA
Monitor
0YYYYYY
1Y-YYYY
2Y--YYY
3Y--YYY
4Y---YY