Datasheet

499
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
DMAC_SADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx
register is left unchanged. The DMAC transfer continues until the DMAC samples the DMAC_CTRLAx,
DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match that described in Row 1 of
Table 31-3 on page 482. The DMAC then knows that the previous buffer transferred was the last buffer in the
DMAC transfer.
The DMAC transfer might look like that shown in Figure 31-15 on page 499. Note that the destination address is
decrementing.
Figure 31-15.DMAC Transfer with Linked List Source Address and Contiguous Destination Address
The DMAC transfer flow is shown in Figure 31-16 on page 500.
SADDR(2)
SADDR(1)
SADDR(0)
DADDR(2)
DADDR(1)
DADDR(0)
Buffer 2
Buffer 1
Buffer 0
Buffer 0
Buffer 1
Buffer 2
Address of
Source Layer
Address of
Destination Layer
Source Buffers
Destination Buffers