Datasheet

494
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Figure 31-12.DMAC Transfer Flow for Replay Mode at Source and Linked List Destination Address
Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 11)
1. Read the Channel Handler Status register to choose a free (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading to the Interrupt Status
Register.
3. Program the following channel registers:
1. Write the starting source address in the DMAC_SADDRx register for channel x.
2. Write the starting destination address in the DMAC_DADDRx register for channel x.
3. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 11 as shown in Table 31-3
on page 482. Program the DMAC_DSCRx register with ‘0’. DMAC_CTRLBx.AUTO field is set to ‘1’ to
enable automatic mode support.
4. Write the control information for the DMAC transfer in the DMAC_CTRLBx and DMAC_CTRLAx register for
channel x. For example, in this register, you can program the following:
 i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control
device by programming the FC of the DMAC_CTRLBx register.
 ii. Set up the transfer characteristics, such as:
 Transfer width for the source in the SRC_WIDTH field.
 Transfer width for the destination in the DST_WIDTH field.
 Source AHB master interface layer in the SIF field where source resides.
 Destination AHB master interface master layer in the DIF field where destination resides.
Channel enabled by
software
LLI Fetch
yes
no
Hardware reprograms
DADDRx, CTRLAx, CTRLBx, DSCRx
DMAC buffer transfer
Writeback of control
status information in LLI
Reload SADDRx
Buffer Transfer Completed
Interrupt generated here
DMAC Chained Buffer Transfer
Completed Interrupt generated here
Channel disabled by
hardware
Is DMAC in
Row 1 of
DMAC State Machine Table?