Datasheet

492
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals.
This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits,
respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘0’ activates the software handshaking interface source/destina-
tion requests.
2. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshak-
ing interface to the source and destination peripheral. This requires programming the SRC_PER and
DST_PER bits, respectively.
5. Make sure that the LLI.DMAC_CTRLBx register locations of all LLIs in memory (except the last one) are set as
shown in Row 6 of Table 31-3 on page 482 while the LLI.DMAC_CTRLBx register of the last Linked List item must
be set as described in Row 1 of Table 31-3. Figure 31-5 on page 481 shows a Linked List example with two list
items.
6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except the last one) are non-zero
and point to the next Linked List Item.
7. Make sure that the LLI.DMAC_DADDRx register locations of all LLIs in memory point to the start destination buffer
address proceeding that LLI fetch.
8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTRLA register locations of all LLIs in memory
is cleared.
9. If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for
channel x.
10. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP is enabled), program the DMAC_DPIPx register
for channel x.
11. Clear any pending interrupts on the channel from the previous DMAC transfer by reading to the DMAC_EBCISR
register.
12. Program the DMAC_CTLx and DMAC_CFGx registers according to Row 6 as shown in Table 31-3 on page 482.
13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item.
14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. The
transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled.
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note: The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI. DMAC_LLPx LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The LLI.DMAC_SADDRx register, although fetched, is not used.
16. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-
memory peripherals). DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer
and carries out the buffer transfer.
17.
The DMAC_CTRLAx register is written out to the system memory. The DMAC_CTRLAx register is written out to the
same location on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is the location of
the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer.
Only
DMAC_CTRLAx register is written out, because only the DMAC_CTRLAx.BTSIZE and
DMAC_CTRLAx.DONE fields
have been updated by hardware within the DMAC.
The LLI.DMAC_CTRLAx.DONE bit is asserted to indicate buffer
completion. Therefore, the software can poll the LLI.DMAC_CTRLAx.DONE field of the DMAC_CTRLAx register in
the LLi to ascertain when a buffer transfer has completed.
Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the polled LLI.DMAC_CTRLAx.DONE bit is asserted,
then this buffer transfer has completed. This LLI.DMAC_CTRLA.DONE bit was cleared at the start of the
transfer.