Datasheet

488
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Figure 31-8. DMAC Transfer Flow for Source and Destination Linked List Address
Channel enabled by
software
LLI Fetch
Hardware reprograms
SADDRx, DADDRx, CTRLA/Bx, DSCRx
DMAC buffer transfer
Writeback of DMAC_CTRLAx
register in system memory
Is DMAC in
Row 1 of
DMAC State Machine Table?
Channel disabled by
hardware
Chained Buffer Transfer Completed
Interrupt generated here
DMAC Chained Buffer Transfer
Completed Interrupt generated here
yes
no