Datasheet

486
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
17. The DMAC does not wait for the buffer interrupt to be cleared, but continues fetching the next LLI from the memory
location pointed to by current DMAC_DSCRx register and automatically reprograms the DMAC_SADDRx,
DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers. The DMAC transfer
continues until the DMAC determines that the DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer
transfer match described in Row 1 of Table 31-3 on page 482. The DMAC then knows that the previous buffer
transferred was the last buffer in the DMAC transfer. The DMAC transfer might look like that shown in Figure 31-6
on page 486.
Figure 31-6. Multi-buffer with Linked List Address for Source and Destination
If the user needs to execute a DMAC transfer where the source and destination address are contiguous but the amount
of data to be transferred is greater than the maximum buffer size DMAC_CTRLAx.BTSIZE, then this can be achieved
using the type of multi-buffer transfer as shown in Figure 31-7 on page 487.
SADDR(2)
SADDR(1)
SADDR(0)
DADDR(2)
DADDR(1)
DADDR(0)
Buffer 2
Buffer 1
Buffer 0
Buffer 0
Buffer 1
Buffer 2
Address of
Source Layer
Address of
Destination Layer
Source Buffers Destination Buffers