Datasheet

474
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
31.2.1 DMA Controller 0
 Two Masters
 Embeds 8 channels
 64-byte FIFO for channel 0, 16-byte FIFO for Channel 1 to 7
 Features:
 Linked List support with Status Write Back operation at End of Transfer
 Word, HalfWord, Byte transfer support.
 Memory to memory transfer
 Peripheral to memory
 Memory to peripheral
The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the
peripherals below. The hardware interface numbers are also given in Table 31-1.
Table 31-1. DMA Channel Definition
Instance name T/R
DMA Channel HW
Interface Number
HSMCI0 RX/TX 0
SPI0 TX 1
SPI0 RX 2
USART0 TX 3
USART0 RX 4
USART1 TX 5
USART1 RX 6
TWI0 TX 7
TWI0 RX 8
TWI2 TX 9
TWI2 RX 10
UART0 TX 11
UART0 RX 12
SSC TX 13
SSC RX 14