Datasheet

465
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
30.7.6 DDRSDRC Timing Parameter 2 Register
Name: DDRSDRC_TPR2
Address: 0xFFFFE814
Access: Read-write
Reset: See Table 30-16
This register can only be written if the WPEN bit is cleared in “DDRSDRC Write Protect Mode Register” on page 471.
• TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit”.
The Reset Value is 2 cycles.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 15.
Note: This field is found only in DDR2-SDRAM devices.
• TXARDS: Exit Active Power Down Delay to Read Command in Mode “Slow Exit”.
The Reset Value is 6 cycles.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 15.
Note: This field is found only in DDR2-SDRAM devices.
• TRPA: Row Precharge All Delay
The Reset Value is 0 cycle.
This field defines the delay between a Precharge ALL banks Command and another command in number of cycles. Number of
cycles is between 0 and 15.
Note: This field is found only in DDR2-SDRAM devices.
• TRTP: Read to Precharge
The Reset Value is 2 cycles.
This field defines the delay between Read Command and a Precharge command in number of cycle.
Number of cycles is between 0 and 7.
• TFAW: Four Active window
The Reset Value is 4 cycles.
DDR2 devices with 8-banks (1Gb or larger) have an additional requirement: t
FAW
. This requires that no more than four
ACTIVATE commands may be issued in any given t
FAW
(MIN) period.
Number of cycles is between 0 and 15.
31 30 29 28 27 26 25 24
–– ––––––
23 22 21 20 19 18 17 16
–– –– TFAW
15 14 13 12 11 10 9 8
TRTP TRPA
76543210
TXARDS TXARD