Datasheet

316
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
25.7.3 Bus Matrix Priority Registers A For Slaves
Name: MATRIX_PRAS0...MATRIX_PRAS9
Address: 0xFFFFDE80 [0], 0xFFFFDE88 [1], 0xFFFFDE90 [2], 0xFFFFDE98 [3], 0xFFFFDEA0 [4], 0xFFFFDEA8 [5],
0xFFFFDEB0 [6], 0xFFFFDEB8 [7], 0xFFFFDEC0 [8], 0xFFFFDEC8 [9]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the “Write Protection Mode Register” .
• MxPR: Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
All the masters programmed with the same MxPR value for the slave make up a priority pool.
Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools.
Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2).
See “Arbitration Priority Scheme” on page 308 for details.
31 30 29 28 27 26 25 24
–– M7PR –– M6PR
23 22 21 20 19 18 17 16
–– M5PR –– M4PR
15 14 13 12 11 10 9 8
–– M3PR –– M2PR
76543210
–– M1PR –– M0PR