Datasheet

198
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
22.13.11PMC Master Clock Register
Name: PMC_MCKR
Address: 0xFFFFFC30
Access: Read-write
• CSS: Master/Processor Clock Source Selection
• PRES: Master/Processor Clock Prescaler
• MDIV: Master Clock Division
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––PLLADIV2–– MDIV
76543210
–PRES––CSS
Value Name Description
0 SLOW_CLK Slow Clock is selected
1 MAIN_CLK Main Clock is selected
2 PLLA_CLK PLLACK/PLLADIV2 is selected
3 UPLL_CLK UPLL Clock is selected
Value Name Description
0 CLOCK Selected clock
1 CLOCK_DIV2 Selected clock divided by 2
2 CLOCK_DIV4 Selected clock divided by 4
3 CLOCK_DIV8 Selected clock divided by 8
4 CLOCK_DIV16 Selected clock divided by 16
5 CLOCK_DIV32 Selected clock divided by 32
6 CLOCK_DIV64 Selected clock divided by 64
7 CLOCK_DIV3 Selected clock divided by 3
Value Name Description
0EQ_PCK
Master Clock is Prescaler Output Clock divided by 1.
Warning: DDRCK is not available.
1PCK_DIV2
Master Clock is Prescaler Output Clock divided by 2.
DDRCK is equal to MCK.
2PCK_DIV4
Master Clock is Prescaler Output Clock divided by 4.
DDRCK is equal to MCK.
3PCK_DIV3
Master Clock is Prescaler Output Clock divided by 3.
DDRCK is equal to MCK.