Datasheet

1141
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Electrical Characteristics:
Added Section 46.12 “USB Transceiver Characteristics” (extracted from SAM9G15 - 11052C: Section 45.12 USB
Transceiver Characteristics).
Section 46.5 “Main Oscillator Characteristics”, replaced minimum CCRYSTAL value of 17.5 with 15 in Table 46-7
“Main Oscillator Characteristics” and in the corresponding note. Updated the related values in the same note.
Section 46.5.1 “Crystal Oscillator Characteristics”, added maximum and minimum CCRYSTAL values for ESR in
Table 46-8 “Crystal Characteristics”.
Section 46.2 “DC Characteristics”, updated RPULLUP parameter characteristics in Section 46-2 “DC
Characteristics”.
Replaced “Input Leakage Current” with “Input Peak Current” in Table 46-26 “Analog Inputs”.
8016
8098
8147
rfo
Mechanical Overview:
Updated the table title in Table 47-4 “Package Information”.8186
Errata:
Section 49.1 “External Bus Interface (EBI)”, updated the problem description and fix/ workaround.
Removed sections concerning PIO and RTC.
Added Section 49.2 “Reset Controller (RSTC)”, Section 49.2.2 “Static Memory Controller (SMC)”, and Section
49.3 “USB High Speed Host Port (UHPHS) and Device Port (UDPHS)”.
Removed “Boot Sequence Controller (BSC)” section (see “Boot Strategies” and “BSC” above for the related
modifications).
8250
rfo
Doc. Rev.
11054B Comments
Change
Request
Ref.
DMAC:
Section 31.1 “Description”, FIFO size table removed.
Section 31-4 “Register Mapping” , added ‘USART3 TX 14’ and ‘USART3 RX 15’.
8004
8081
PMC:
Figure 22-2 “General Clock Block Diagram”:
- Prescaler /1,/2,/4,.../64 --> Prescaler /1,/2,/3,/4,.../64 (for Master Clock Controller.)
- SysClk DDR --> 2x MCK, and connection added above with /2 block and DDRCK.
Figure 22-3 “Switch Master Clock from Slow Clock to PLL Clock” , ...and the division by 6 --> ...and the division
by 3.
Section 22.13.11 “PMC Master Clock Register”:
- Value 7 for PRES field no more reserved, now with CLOCK_DIV3, Selected clock divided by 3.
- MDIV field, references to ‘SysClk DDR’ removed (x4).
Section 22.2 “Embedded Characteristics”, 266 MHz DDR system clock --> 133MHz DDR system clock.
Then DDR system clock --> DDR clock.
7974
7975
Doc. Rev.
11054C Comments
Change
Request
Ref.
(1)