Datasheet

1136
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
PMECC:
Figure 27-2 “Software/Hardware Multibit Error Correction Dataflow”, “READ PAGE” and “PROGRAM PAGE”
positions swapped in the flow chart.
Figure 27-5 “Read Operation with Spare Decoding”, configuration revised as ”...SPAREEN set to One and AUTO
set to Zero.”
Section 27.2 “Embedded Characteristics”, added a line about supporting 8-bit Nand Flash data bus.
Section 27.6.11 “PMECC Interrupt Status Register”, replaced duplicate bits 31 - 24 with missing 7 - 0 in the
PMECC_ISR register table.
7495
8403
rfo
PMERRLOC:
Section 28.5.10 “Error Location SIGMAx Register”, “SIGMAN” bitfield name replaced with “SIGMAx” in the
PMERRLOC_SIGMAx [x=0..24] register table.
8339
SMC:
Replaced “...turned out...” with “...switched to output mode...” in the first paragraphes in Section 29.9.4.1 “Write is
Controlled by NWE (WRITE_MODE = 1)” and Section 29.9.4.2 “Write is Controlled by NCS (WRITE_MODE =
0)”.
7925
DDRSDRC:
Section 30.2 “Embedded Characteristics”, removed duplicate reference to DDR2-SDRAM. 8146
DMAC:
Section 31.4.5.1 “Programming Examples”, value ‘1’ --> ‘0’ for a masked BTC (DMAC_EBCIMR.BTCx = ‘0’) in
“Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10)” .
Updated names:
- ‘Buffer Complete Interrupt’ --> ‘Buffer Transfer Completed Interrupt’
- ‘Chained Buffer Interrupt’ --> ‘Chained Buffer Transfer Completed Interrupt’
- ‘Transfer Complete Interrupt’ --> ‘Chained Buffer Transfer Completed Interrupt’
- KEEPON[n] --> KEEPx, STALLED[n] --> STALx, ENABLE[n] --> ENAx, SUSPEND[n] --> SUSPx, RESUME[n] -
-> RESx, EMPTY[n] --> EMPTx.
- Read the Channel Enable register --> Read the Channel Handler Status register.
Detailed bitfield acronyms when missing.
Updated Section 31.2 “Embedded Characteristics”:
- updated the list of embedded characteristics
- removed Section 31.2.1 DMA Controller 0 and Section 31.2.1 DMA Controller 1.
Section 31.7.16 “DMAC Channel x [x = 0..7] Control A Register”, updated SCSIZE and DCSIZE bitfield tables.
Section 31.7.21 “DMAC Write Protect Mode Register”, updated the descriptions of WPEN and WPKEY bitfields:
replaced the wrong values 0x444D4143 and 0x50494F with 0x444D41, and replaced ‘(“DMAC” in ASCII)’ with
‘(“DMA” in ASCII)’.
Section 31.7.2 “DMAC Enable Register”, Section 31.7.15 “DMAC Channel x [x = 0..7] Descriptor Address
Register”, Section 31.7.16 “DMAC Channel x [x = 0..7] Control A Register”, and Section 31.7.17 “DMAC Channel
x [x = 0..7] Control B Register”, added respectively descriptions of the following bitfields:
- “ENABLE: General Enable of DMA”
- “DSCR_IF: Descriptor Interface Selection”
- “DONE: Current Descriptor Stop Command and Transfer Completed Memory Indicator”
- “IEN: Interrupt Enable Not”
Updated the last paragraph in Section 31.4.4.3 “Ending Multi-buffer Transfers”.
7393
rfo
8143
8404
rfo
8441
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