Datasheet

1122
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Notes: 1. 1.8V domain: V
DDIO
from 1.65V to 1.95V, maximum external capacitor = 20pF
2. 3.3V domain: V
DDIO
from 3.0V to 3.6V, maximum external capacitor = 40pF.
Table 46-46. USART SPI Timings
Symbol Parameter Conditions Min Max Unit
Master Mode
SPI
0
SCK Period
1.8V domain
(1)
3.3V domain
(2)
MCK/6 ns
SPI
1
Input Data Setup Time
1.8V domain
(1)
3.3V domain
(2)
0.5 × MCK + 4.1
0.5 × MCK + 3.8
ns
SPI
2
Input Data Hold Time
1.8V domain
(1)
3.3V domain
(2)
1.5 × MCK + 0.9
1.5 × MCK + 1.1
ns
SPI
3
Chip Select Active to Serial Clock
1.8V domain
(1)
3.3V domain
(2)
1.5 × SCK - 2.0
1.5 × SCK - 2.6
ns
SPI
4
Output Data Setup Time
1.8V domain
(1)
3.3V domain
(2)
0
0
7.6
8.0
ns
SPI
5
Serial Clock to Chip Select Inactive
1.8V domain
(1)
3.3V domain
(2)
1 × SCK - 6.7
1 × SCK - 7.5
ns
Slave Mode
SPI
6
SCK falling to MISO
1.8V domain
(1)
3.3V domain
(2)
3.7
2.9
19.9
16.9
ns
SPI
7
MOSI Setup time before SCK rises
1.8V domain
(1)
3.3V domain
(2)
2 × MCK + 3.4
2 × MCK + 3.1
ns
SPI
8
MOSI Hold time after SCK rises
1.8V domain
(1)
3.3V domain
(2)
1.6
1.4
ns
SPI
9
SCK rising to MISO
1.8V domain
(1)
3.3V domain
(2)
3.4
2.7
19.4
16.5
ns
SPI
10
MOSI Setup time before SCK falls
1.8V domain
(1)
3.3V domain
(2)
2 × MCK + 2.9
2 × MCK + 2.8
ns
SPI
11
MOSI Hold time after SCK falls
1.8V domain
(1)
3.3V domain
(2)
2.1
1.8
ns
SPI
12
NPCS0 setup to SCK rising
1.8V domain
(1)
3.3V domain
(2)
2.5 × MCK + 1.4
2.5 × MCK + 1.2
ns
SPI
13
NPCS0 hold after SCK falling
1.8V domain
(1)
3.3V domain
(2)
1.5 × MCK + 2.5
1.5 × MCK + 2.2
ns
SPI
14
NPCS0 setup to SCK falling
1.8V domain
(1)
3.3V domain
(2)
2.5 × MCK + 0.9
2.5 × MCK + 0.8
ns
SPI
15
NPCS0 hold after SCK rising
1.8V domain
(1)
3.3V domain
(2)
1.5 × MCK + 2.1
1.5 × MCK + 1.9
ns