Datasheet

1116
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Notes: 1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or
5 or 7 (Receive Start Selection), two periods of the MCK must be added to timings.
2. For output signals (TF, TD, RF), minimum and maximum access times are defined. The minimum access time is the
time between the TK (or RK) edge and the signal change. The maximum access time is the time between the TK
edge and the signal stabilization. Figure 46-23 illustrates minimum and maximum accesses for SSC0. The same
applies to SSC1, SSC4, and SSC7, SSC10 and SSC13.
3. 1.8V domain: V
DDIO
from 1.65V to 1.95V, maximum external capacitor = 20 pF.
4. 3.3V domain: V
DDIO
from 3.0V to 3.6V, maximum external capacitor = 30 pF.
Table 46-40. SSC Timings
Symbol Parameter Conditions Min Max Unit
Transmitter
SSC
0
TK edge to TF/TD (TK output, TF output)
1.8V domain
(3)
3.3V domain
(4)
-5.6
-4.6
5.8
4.9
ns
SSC
1
TK edge to TF/TD (TK input, TF output)
1.8V domain
(3)
3.3V domain
(4)
3.0
2.3
15.7
11.4
ns
SSC
2
TF setup time before TK edge (TK output)
1.8V domain
(3)
3.3V domain
(4)
14.0
9.9
ns
SSC
3
TF hold time after TK edge (TK output)
1.8V domain
(3)
3.3V domain
(4)
0
0
ns
SSC
4
(1)
TK edge to TD (TK output, TF input)
1.8V domain
(3)
3.3V domain
(4)
-5.6 (+2 × t
CPMCK
)
(1)(4)
-4.6 (+2 × t
CPMCK
)
(1)(4)
5.7 (+2 × t
CPMCK
)
(1)(4)
4.7 (+2 × t
CPMCK
)
(1)(4)
ns
SSC
5
TF setup time before TK edge (TK input)
1.8V domain
(3)
3.3V domain
(4)
0ns
SSC
6
TF hold time after TK edge (TK input)
1.8V domain
(3)
3.3V domain
(4)
t
CPMCK
ns
SSC
7
(1)
TK edge to TD (TK input, TF input)
1.8V domain
(3)
3.3V domain
(4)
3.0 (+3 × t
CPMCK
)
(1)(4)
2.3 (+3 × t
CPMCK
)
(1)(4)
15.5(+3 × t
CPMCK
)
(1)(4)
11.1(+3 × t
CPMCK
)
(1)(4)
ns
Receiver
SSC
8
RF/RD setup time before RK edge (RK input)
1.8V domain
(3)
3.3V domain
(4)
0ns
SSC
9
RF/RD hold time after RK edge (RK input)
1.8V domain
(3)
3.3V domain
(4)
t
CPMCK
ns
SSC
10
RK edge to RF (RK input)
1.8V domain
(3)
3.3V domain
(4)
2.6
2.0
15.2
10.9
ns
SSC
11
RF/RD setup time before RK edge (RK output)
1.8V domain
(3)
3.3V domain
(4)
14.1 - t
CPMCK
10.0 - t
CPMCK
ns
SSC
12
RF/RD hold time after RK edge (RK output)
1.8V domain
(3)
3.3V domain
(4)
t
CPMCK
- 2.5
t
CPMCK
- 1.8
ns
SSC
13
RK edge to RF (RK output)
1.8V domain
(3)
3.3V domain
(4)
-5.9
-4.9
5.2
4.3
ns