Datasheet

1102
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
46.13 Analog-to-Digital Converter (ADC)
Note: 1. The Track-and-Hold Acquisition Time is given by: TTH (ns) = 500 + (0.12 × Z
IN
)(Ω)
The ADC internal clock is divided by 2 in order to generate a clock with a duty cycle of 75%. So the maximum conver-
sion time is given by:
The full speed is obtained for an input source impedance of < 50 Ω maximum, or TTH = 500 ns.
In order to make the TSADC work properly, the SHTIM field in TSADCC Mode Register is to be calculated according
to this Track and Hold Acquisition Time, also called Sampled and Hold Time.
Table 46-24. Channel Conversion Time and ADC Clock
Parameter Conditions Min Typ Max Unit
ADC Clock Frequency 10-bit resolution mode 13.2 MHz
Startup Time Return from Idle Mode 40 µs
Track and Hold Acquisition Time (TTH) ADC Clock = 13.2 MHz
(1)
0.5 µs
Conversion Time (TCT)
ADC Clock = 13.2 MHz
(1)
ADC Clock = 5 MHz
(1)
1.74
4.6
µs
Throughput Rate
ADC Clock = 13.2 MHz
(1)
ADC Clock = 5 MHz
(1)
440
192
kSPS
TCT µs()
23
f
clk
--------
MHz()=
Table 46-25. External Voltage Reference Input
Parameter Conditions Min Typ Max Unit
ADVREF Input Voltage Range 2.4 VDDANA V
ADVREF Average Current 600 µA
Current Consumption on VDDANA 600 µA
Table 46-26. Analog Inputs
Parameter Conditions Min Typ Max Unit
Input Voltage Range 0 ADVREF V
Input Peak Current 2.5 mA
Input Capacitance 710pF
Input Impedance 50 Ω
Table 46-27. Transfer Characteristics
Parameter Conditions Min Typ Max Unit
Resolution 10 bit
Integral Non-linearity ±2LSB
Differential Non-linearity
ADC Clock = 13.2 MHz ±2
LSB
ADC Clock = 5 MHz ±0.9
Offset Error ±10 mV
Gain Error
ADC Clock = 13.2 MHz ±3
LSB
ADC Clock = 5 MHz ±2