Datasheet

34
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64
– Support for two PDC channels with connection to receiver and transmitter
• Debug Communication Channel Support
– Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from
the ARM Processor’s ICE Interface
9.15 Chip Identification
• Chip ID: 0x019B03A0
• JTAG ID: 0x05B2003F
• ARM926 TAP ID: 0x0792603F
9.16 PIO Controllers
• 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, controlling a maximum of 118 I/O Lines
• Each PIO Controller controls up to 32 programmable I/O Lines
– PIOA has 32 I/O Lines
– PIOB has 32 I/O Lines
– PIOC has 32 I/O Lines
– PIOD has 22 I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of two peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
– Input change interrupt
– Glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
• Synchronous output, provides Set and Clear of several I/O lines in a single write
10. Peripherals
10.1 Peripheral Mapping
As shown in Figure 8-1, the Peripherals are mapped in the upper 256M bytes of the address
space between the addresses 0xFFFA 0000 and 0xFFFC FFFF.
Each User Peripheral is allocated 16K bytes of address space.