Datasheet

33
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64
• Two hundred year calendar
• Programmable Periodic Interrupt
• Alarm and update parallel load
• Control of alarm and update Time/Calendar Data In
9.12 General-Purpose Backed-up Registers
• Four 32-bit backup general-purpose registers
9.13 Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
• One External Sources plus the Fast Interrupt signal
• 8-level Priority Controller
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
•Protect Mode
– Easy debugging by preventing automatic operations when protect modeIs are
enabled
•Fast Forcing
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
processor
9.14 Debug Unit
• Composed of two functions
–Two-pin UART
– Debug Communication Channel (DCC) support
•Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes