Datasheet

31
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64
Figure 9-2. Clock Generator Block Diagram
9.6 Slow Clock Selection
9.6.1 Description
The AT91SAM9R64/RL64 slow clock can be generated either by an external 32768Hz crystal or
the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to accept an external
slow clock on XIN32.
Configuration is located in the slow clock control register (SCKCR) located at address
0xFFFFFD50 in the backed up part of the system controller and so is preserved while VDDBU is
present.
Refer to the “Clock Generator” section for more details.
9.7 Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
• the Processor Clock PCK
• the Master Clock MCK, in particular to the Matrix and the memory interfaces
• the USB Device HS Clock HSCK
• independent peripheral clocks, typically at the frequency of MCK
• two programmable clock outputs: PCK0 and PCK1
This allows the software control of five flexible operating modes:
• Normal Mode, processor and peripherals running at a programmable frequency
• Idle Mode, processor stopped waiting for an interrupt
• Slow Clock Mode, processor and peripherals running at low frequency
Power
Management
Controller
XIN
XOUT
Main Clock
MAINCK
ControlStatus
PLL and
Divider
PLLRCA
PLL Clock
PLLCK
12M Main
Oscillator
UPLL
(PLLB)
On Chip
RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
Clock Generator
RCEN
HSCK
OSCSEL
OSC32EN
OSC32BYP