Datasheet

30
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64
9.3 Reset Controller
The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on
VDDCORE.
The Reset Controller is capable to return to the software the source of the last reset, either a
general reset (VDDBU rising), a wake-up reset (VDDCORE rising), a software reset, a user
reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin output. It is
capable to shape a reset signal for the external devices, simplifying to a minimum connection of
a push-button on the NRST pin to implement a manual reset.
The configuration of the Reset Controller is saved as supplied on VDDBU.
9.4 Shutdown Controller
The Shutdown Controller is supplied on VDDBU and allows a software-controllable shut down of
the system through the pin SHDN. An input change of the WKUP pin or an alarm releases the
SHDN pin, and thus wakes up the system power supply.
9.5 Clock Generator
The Clock Generator is made up of:
• One low-power 32768 Hz Slow Clock Oscillator with bypass mode
• One low-power RC oscillator
• One 12 MHz Main Oscillator, which can be bypassed
• One 480 MHz PLL (UPLL or PLLB) providing a clock for the USB High Speed Device
Controller
• One 80 to 240 MHz programmable PLL, providing the PLL Clock (PLLCK). This PLL has an
input divider to offer a wider range of output frequencies from the 12 MHz input, the only
limitation being the lowest input frequency shall be higher or equal to 1 MHz.