Datasheet

21
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64
a. TWI0 Transmit Channel
b. DBGU Transmit Channel
c. USART3 Transmit Channel
d. USART2 Transmit Channel
e. USART1 Transmit Channel
f. USART0 Transmit Channel
g. AC97 Transmit Channel
h. SPI Transmit Channel
i. SSC1 Transmit Channel
j. SSC0 Transmit Channel
k. TWI0 Receive Channel
l. DBGU Receive Channel
m. ADC Receive Channel
n. USART3 Receive Channel
o. USART2 Receive Channel
p. USART1 Receive Channel
q. USART0 Receive Channel
r. AC97 Receive Channel
s. SPI Receive Channel
t. SSC1 Receive Channel
u. SSC0 Transmit Channel
v. MCI Receive/Transmit Channel
7.6 DMA Controller
• Acting as one Matrix Master
• Embeds 2 channels
• 16 bytes/FIFO for Channel Buffering
• Linked List support with Status Write Back operation at End of Transfer
• Word, Half-word, Byte transfer support
7.7 Debug and Test Features
• ARM926 Real-time In-circuit Emulator
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
• Debug Unit
–Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins