Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller BGA 144 (13x13) 16/32-Bit 240 MHz I/O number 49

Features

• Incorporates the ARM926EJ-S

™

ARM

Thumb

Processor

– DSP Instruction Extensions

– ARM Jazelle

Technology for Java

Acceleration

– 4 Kbyte Data Cache, 4 Kbyte Instruction Cache, Write Buffer

– 265 MIPS at 240 MHz

– Memory Management Unit

– EmbeddedICE

™

In-circuit Emulation, Debug Communication Channel Support

• Multi-layer AHB Bus Matrix for Large Bandwidth Transfers

– Six 32-bit-layer Matrix

– Boot Mode Select Option, Remap Command

• One 32-KByte internal ROM, Single-cycle Access at Maximum Speed

• One 64-KByte internal SRAM, Single-cycle Access at Maximum Speed

– 4 Blocks of 16 Kbytes Configurable in TCM or General-purpose SRAM on the AHB

Bus Matrix

– Single-cycle Accessible on AHB Bus at Bus Speed

– Single-cycle Accessible on TCM Interface at Processor Speed

• 2-channel DMA

– Memory to Memory Transfer

– 16 Bytes FIFO

– LInked List

• External Bus Interface (EBI)

– EBI Supports SDRAM, Static Memory, ECC-enabled NAND Flash and

CompactFlash

• LCD Controller (for AT91SAM9RL64 only)

– Supports Passive or Active Displays

– Up to 24 Bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode

– Up to 16M Colors in TFT Mode, Resolution Up t

o 2048x2048, Virtual Screen

Support

• High Speed (480 Mbit/s) USB 2.0 Device Controller

– On-Chip High Speed Transceiver, UTMI+ Physical Interface

– Integrated FIFOs and Dedicated DMA

– 4 Kbyte Configurable Integrated DPRAM

• Fully-featured System Controller, including

– Reset Controller, Shutdown Controller

– Four 32-bit Battery Backup Registers for a Total of 16 Bytes

– Clock Generator and Power Management Controller

– Advanced Interrupt Controller and Debug Unit

– Periodic Interval Timer, Watchdog Timer and Real-time Timer and Real-time Clock

• Reset Controller (RSTC)

– Based on Two Power-on Reset Cells

– Reset Source Identification and Reset Output Control

• Shutdown Controller (SHDC)

– Programmable Shutdown Pin Control and Wake-up Circuitry

• Clock Generator (CKGR)

– Selectable 32768 Hz Low-power Oscillator or Internal Low-power RC Oscillator on

Battery Backup Power Supply, Providing a Permanent Slow Clock

– 12 MHz On-chip Oscillator for Main System Clock and USB Clock

– One PLL up to 240 MHz

6289CS–ATARM–28-May-09

AT91 ARM

Thumb

Microcontrollers

AT91SAM9R64

AT91SAM9RL64

Summary

Summary of content (52 pages)

PAGE 1
Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor • • • • • • • • • • • – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 4 Kbyte Data Cache, 4 Kbyte Instruction Cache, Write Buffer – 265 MIPS at 240 MHz – Memory Management Unit – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support Multi-layer AHB Bus Matrix for Large Bandwidth Transfers – Six 32-bit-layer Matrix – Boot Mode Select Option, Remap Command One 32-KByte internal ROM, Single-
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– One PLL 480 MHz Optimized for USB HS • Power Management Controller (PMC) • • • • • • • • • • • • • • • • • 2 – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Two Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – One External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug C
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AT91SAM9R64/RL64 – – – – • • • • Master, Multi-master and Slave Mode Operation Bit Rate: Up to 400 Kbits General Call Supported in Slave Mode Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only (TWI0 only) SAM-BA® Boot Assistant – Default Boot Program – Interface with SAM-BA Graphic User Interface IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies: – 1.08 to 1.32V for VDDCORE, VDDUTMIC, VDDPLLB and VDDBU – 3.0V to 3.
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Table 1-1.
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6289CS–ATARM–28-May-09 12 MHz OSC XIN XOUT POR VDDBU NRST MCI PDC TWI0 PDC ROM 32K Bytes USART0 USART1 USART2 USART3 PDC D G S SPI PDC APB PWM Peripheral Bridge TC0 TC1 TC2 SSC0 PDC EF NA AN VR DA ND AD VD G S T G 0 1 2 TR AD AD AD D A TS 3-channel 10-bit ADC PDC 2-channel DMA 0 0 0 0 0 K0 TK TF TD RD RF R Peripheral DMA Controller 5-layer AHB Bus Matrix DMA USB Device HS HS UTMI Transceiver BM 1 S1 3 3 0 1 3 0 2 A0 B0 S1 CK SI ISO M M M TS RT XD XD LK LK O O W PC P O R T C
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POR VDDBU NRST PIOD PIOC TD TDI O TM S T C RTK CK NT RS T J T AG SE L MCI TWI0 PDC PDC TWI1 I ROM 32K Bytes USART0 USART1 USART2 USART3 PDC D ICache DCache 4 Kbytes 4 Kbytes SRAM 64K Bytes TCM Interface ITCM DTCM ARM926EJ-S Processor In-Circuit Emulator JTAG Selection and Boundary Scan BM S SPI PDC APB PWM TC0 TC1 TC2 Peripheral Bridge AC97 PDC Peripheral DMA Controller 6-layer AHB Bus Matrix DMA USB Device HS HS UTMI Transceiver SSC0 SSC1 PDC Touch Screen Controller 6
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AT91SAM9R64/RL64 3. Signal Description Table 3-1 gives details on the signal name classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Comments Power Supplies VDDIOM EBI I/O Lines Power Supply Power 1.65V to 3.6V VDDIOP Peripherals I/O Lines Power Supply Power 3.0V to 3.6V VDDUTMII USB UTMI+ Interface Power Supply Power 3.0V to 3.6V VDDUTMIC USB UTMI+ Core Power Supply Power 1.08V to 1.
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Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level NTRST Test Reset Signal Input Low Pull-up resistor. Low Pull-up resistor Comments Reset/Test NRST Microcontroller Reset TST Test Mode Select BMS I/O Boot Mode Select Input Pull-down resistor Input Must be connected to GND or VDDIOP.
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AT91SAM9R64/RL64 Table 3-1.
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Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Comments AC97 Controller - AC97C AC97RX AC97 Receive Signal Input Not present on AT91SAM9R64. AC97TX AC97 Transmit Signal Output Not present on AT91SAM9R64. AC97FS AC97 Frame Synchronization Signal Output Not present on AT91SAM9R64. AC97CK AC97 Clock signal Input Not present on AT91SAM9R64.
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AT91SAM9R64/RL64 Table 3-1.
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4. Package and Pinout The AT91SAM9R64 is available in a 144-ball BGA package. The AT91SAM9RL64 is available in a 217-ball LFBGA package. 4.1 144-ball BGA Package Outline Figure 4-1 shows the orientation of the 144-ball BGA package. Figure 4-1.
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AT91SAM9R64/RL64 4.2 Pinout Table 4-1.
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4.3 217-ball LFBGA Package Outline Figure 4-2 shows the orientation of the 217-ball LFBGA package. Figure 4-2.
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AT91SAM9R64/RL64 4.4 Pinout Table 4-2.
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5. Power Considerations 5.1 Power Supplies The AT91SAM9R64/RL64 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: Power the External Bus Interface; voltage ranges between 1.65V and 1.95V (1.8V nominal) or between 3.0V and 3.6V (3.3V nominal). • VDDIOP pins: Power the Peripherals I/O lines; voltage ranges from 3.0V and 3.6V, 3.3V nominal.
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AT91SAM9R64/RL64 Figure 5-1. Example of PLL and USB Power Supplies VIN VIN 1V2_USB VOUT 10µF CE 0.1µF 1K 10µF ADJ VSS 100K MIC5235YM5 2.2µH 1V2_USB VDDPLLB 0.1µF 2.2µH 1V2_USB VDDUTMIC 0.1µF 2.2µH 3V3 VDDUTMII 0.1µF 5.2 Programmable I/O Lines Power Supplies The power supplies pins VDDIOM support two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories.
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6. I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors. TDO is an output, driven at up to VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. All the JTAG signals are supplied with VDDIOP except JTAGSEL supplied by VDDBU. 6.
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AT91SAM9R64/RL64 ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • DSP Instruction Extensions • 5-Stage Pipeline Architecture: • • • • 7.
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Table 7-1. 7.3 List of Bus Matrix Masters Master 3 Peripheral DMA Controller Master 4 ARM926™ Instruction Master 5 ARM926 Data Matrix Slaves The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 7-2. 7.
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AT91SAM9R64/RL64 a. TWI0 Transmit Channel b. DBGU Transmit Channel c. USART3 Transmit Channel d. USART2 Transmit Channel e. USART1 Transmit Channel f. USART0 Transmit Channel g. AC97 Transmit Channel h. SPI Transmit Channel i. SSC1 Transmit Channel j. SSC0 Transmit Channel k. TWI0 Receive Channel l. DBGU Receive Channel m. ADC Receive Channel n. USART3 Receive Channel o. USART2 Receive Channel p. USART1 Receive Channel q. USART0 Receive Channel r. AC97 Receive Channel s.
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8. Memories Figure 8-1.
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AT91SAM9R64/RL64 A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to 8 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS5.
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• Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0020 0000. • Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters.
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AT91SAM9R64/RL64 When accessed from the AHB, the internal Fast SRAM is single cycle accessible at full matrix speed (MCK). When accessed from the processor’s TCM Interface, they are also single cycle accessible at full processor speed. 8.1.1.2 Internal ROM The AT91SAM9R64/RL64 embeds an Internal ROM, which contains the SAM-BA program. At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0 (BMS =1) after the reset and before the Remap Command. 8.1.
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• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. For optimization purposes, nothing else is done.
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AT91SAM9R64/RL64 8.2.
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9. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface embeds also the registers allowing to configure the Matrix and a set of registers configuring the EBI chip select assignment and the voltage range for external memories. 9.
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AT91SAM9R64/RL64 9.2 Block Diagram Figure 9-1. System Controller Block Diagram System Controller VDDCORE Powered irq0-irq2 fiq periph_irq[2..
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9.3 Reset Controller The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on VDDCORE. The Reset Controller is capable to return to the software the source of the last reset, either a general reset (VDDBU rising), a wake-up reset (VDDCORE rising), a software reset, a user reset or a watchdog reset. The Reset Controller controls the internal resets of the system and the NRST pin output.
PAGE 31
AT91SAM9R64/RL64 Figure 9-2. Clock Generator Block Diagram Clock Generator RCEN On Chip RC OSC XIN32 XOUT32 Slow Clock SLCK Slow Clock Oscillator OSCSEL OSC32EN OSC32BYP XIN Main Clock MAINCK 12M Main Oscillator XOUT UPLL (PLLB) PLLRCA HSCK PLL and Divider Status PLL Clock PLLCK Control Power Management Controller 9.6 9.6.1 Slow Clock Selection Description The AT91SAM9R64/RL64 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator.
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• Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery Figure 9-3. AT91SAM9R64/RL64 Power Management Controller Block Diagram Processor Clock Controller int Master Clock Controller SLCK MAINCK PLLCK PCK Idle Mode Prescaler /1,/2,/4,...,/64 MCK Peripherals Clock Controller periph_clk[..] ON/OFF Programmable Clock Controller SLCK MAINCK PLLCK 9.
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AT91SAM9R64/RL64 • Two hundred year calendar • Programmable Periodic Interrupt • Alarm and update parallel load • Control of alarm and update Time/Calendar Data In 9.12 General-Purpose Backed-up Registers • Four 32-bit backup general-purpose registers 9.
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– Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE Interface 9.15 Chip Identification • Chip ID: 0x019B03A0 • JTAG ID: 0x05B2003F • ARM926 TAP ID: 0x0792603F 9.
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AT91SAM9R64/RL64 10.2 Peripheral Identifiers The Table 10-1 defines the Peripheral Identifiers of the AT91SAM9R64/RL64. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1.
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10.3 10.3.1 Peripheral Interrupts and Clock Control System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-time Timer • the Real-time Clock • the Watchdog Timer • the Reset Controller • the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.3.2 10.
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AT91SAM9R64/RL64 10.4.1 AT91SAM9RL64 PIO Multiplexing 10.4.1.1 Table 10-2.
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10.4.1.2 AT91SAM9RL64 PIO Controller B Multiplexing Table 10-3.
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AT91SAM9R64/RL64 10.4.1.3 Table 10-4.
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10.4.1.4 AT91SAM9RL64 PIO Controller D Multiplexing Table 10-5.
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AT91SAM9R64/RL64 10.4.2 Note: AT91SAM9R64 PIO Multiplexing In Table 10-6, Table 10-7, Table 10-8 and Table 10-9, shaded cells indicate I/O lines that are NOT available on the AT91SAM9R64. 10.4.2.1 Table 10-6.
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10.4.2.2 AT91SAM9R64 PIO Controller B Multiplexing Table 10-7.
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AT91SAM9R64/RL64 10.4.2.3 Table 10-8. AT91SAM9R64 PIO Controller C Multiplexing AT91SAM9R64 Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A Application Usage Peripheral B Reset State Power Supply PC0 TF0 I/O VDDIOP PC1 TK0 I/O VDDIOP PC2PC31 NA 10.4.2.4 Table 10-9.
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11. Embedded Peripherals Overview 11.
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AT91SAM9R64/RL64 – Optional break generation and detection – By 8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication at up to
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– Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels 11.
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AT91SAM9R64/RL64 – Endpoint 0: 64 bytes, 1 bank mode – Endpoint 1 & 2: 1024 bytes, 2 banks mode, HS isochronous capable, DMA – Endpoint 3 & 4: 1024bytes, 3 banks mode, DMA – Endpoint 5 & 6: 1024 bytes, 3 banks mode, HS isochronous capable, DMA 11.10 LCD Controller (LCDC) • Single and Dual scan color and monochrome passive STN LCD panels supported • Single scan active TFT LCD panels supported.
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12. Package Drawings Figure 12-1.
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AT91SAM9R64/RL64 Figure 12-2.
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13. AT91SAM9R64/RL64 Ordering Information Table 13-1.
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AT91SAM9R64/RL64 14. Revision History Doc. Rev Comments 6289CS Product Overview: “Features” on page 1, removed mid-level Embedded Trace Macrocell feature “Features” on page 1, updated figures on CPU speed “Features” on page 1, updated SDIO and MMC version Removed paragraph Section 5.2 “Power Consumption”. Section 6.5 “Shutdown Logic Pins”, removed information on the shutdown pin Section 8.1.2.
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