Datasheet

6289CS–ATARM–28-May-09

AT91SAM9R64/RL64

– Endpoint 0: 64 bytes, 1 bank mode

– Endpoint 1 & 2: 1024 bytes, 2 banks mode, HS isochronous capable, DMA

– Endpoint 3 & 4: 1024bytes, 3 banks mode, DMA

– Endpoint 5 & 6: 1024 bytes, 3 banks mode, HS isochronous capable, DMA

11.10 LCD Controller (LCDC)

• Single and Dual scan color and monochrome passive STN LCD panels supported

• Single scan active TFT LCD panels supported.

• 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported

• Up to 24-bit single scan TFT interfaces supported

• Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays

• 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN

• 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN

• 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT

• Single clock domain architecture

• Resolution supported up to 2048x2048

11.11 Touch Screen Analog-to-digital Converter (TSADCC)

• 6-channel ADC

• Support 4-wire resistive Touch Screen

• 10-bit 384 Ksamples/sec. Successive Approximation Register ADC

• -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity

• Integrated 6-to-1 multiplexer, offering eight independent 3.3V analog inputs

• External voltage reference for better accuracy on low voltage inputs

• Individual enable and disable of each channel

• Multiple trigger sources

– Hardware or software trigger

– External trigger pin

– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger

• Sleep Mode and conversion sequencer

– Automatic wakeup on trigger and back to sleep mode after conversions of all

enabled channels