Datasheet

20
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64
7.3 Matrix Slaves
The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own
arbiter, allowing a different arbitration per slave.
7.4 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the USB Device High speed DMA to the Internal Peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table.
7.5 Peripheral DMA Controller (PDC)
• Acting as one AHB Bus Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
of the processor.
• Next Pointer support, prevents strong real-time constraints on buffer management.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Master 3 Peripheral DMA Controller
Master 4 ARM926
™
Instruction
Master 5 ARM926 Data
Table 7-1. List of Bus Matrix Masters
Table 7-2. List of Bus Matrix Slaves
Slave 0 Internal ROM
Slave 1 Internal SRAM
Slave 2 LCD Controller User Interface
Slave 3 UDP High Speed RAM
Slave 4 External Bus Interface (EBI)
Slave 5 Peripheral Bridge
Table 7-3. AT91SAM9R64/RL64 Master to Slave Access
Masters 0 1 2 3 4 5
Slaves
DMA
Controller
USB HS
Device DMA
LCD
Controller
DMA
Peripheral
DMA
ARM926
Instruction
ARM926
Data
0 Internal ROM X X X X X
1 Internal SRAM X X X X X X
2 LCD Controller User Interface - - - - X X
3 UDP High Speed RAM - - - - X X
4 External Bus Interface X X X X X X
5 Peripheral Bridge X X X - - -