User manual

SAM9N12/CN11-EK User Guide 4-11
11186A–ATARM–29-Nov-12
4.3.10 Serial Peripheral Interface (SPI) Controller
The SAM9N12/CN11 serial processor provides two high-speed Serial Peripheral Interface (SPI) control-
lers. One port is used to interface with the on-board serial DataFlash.
A 3-state buffer is in serial with DataFlash CS signal, with PB1 to give a manually disable manner for
Data
Flash boot.
Figure 4-13. SPI DataFlash
4.3.
11 Two Wire Interface (TWI)
The SAM9N12/CN11 processor has two full speed (400 kHz) master/slave I2C serial controllers. The
cont
rollers are fully compatible with the industry standard I2C interfaces. On the EK board, TWI0 port is
used to interface with serial EEPROM, QTouch device and audio CODEC interface.
SAM9N12/CN11 processor supports TWI EEPROM boot at the device
address of 0x50. On board, the
EEPROM device address is 0x51. Customer needs to dismount R61 and mount R62 as 10 kohms, if
EEPROM boot is needed.
Figure 4-14. EEPROM
R56 0R
R57 0R
R58 0R
VDDIOP0
VDDIOP0
MN9
AT25DF321A
HOLD
7
GND
4
VCC
8
CS
1
SCK
6
SI
5
SO
2
WP
3
PA12
PA11
(SPI0_MOSI)
(SPI0_MIS0)
(SPI0_SPCK)
(SPI0_NPCS0)
C59
100nF
R55
470K
OE_D ataf lash
VDD IOP0
PA14
C58
100nF
MN 8
NL17SZ126
OE
1
VCC
5
GND
3
OUT
4
IN
2
PA13
MN10
AT24C512C-SSHD-T
A0
1
A1
2
WP
7
SCL
6
VCC
8
A3
3
SDA
5
GND
4
VDDIOP0
R61
10K
VDDIOP0VDDIOP0
PA31
PA30
(TWDO)
(TWCKO)
R59
4.7K
VDDIOP0 R62
DNP
R60
4.7K
C60
100nF