Datasheet

928
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
43.8.1 Write Protection Registers
To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write protected by
setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status Register
(US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the SSC Write Protect Mode Register (SSC_WPMR) with the appropriate access key,
WPKEY.
The protected registers are:
 “SSC Clock Mode Register”
 “SSC Receive Clock Mode Register”
 “SSC Receive Frame Mode Register”
 “SSC Transmit Clock Mode Register”
 “SSC Transmit Frame Mode Register”
 “SSC Receive Compare 0 Register”
 “SSC Receive Compare 1 Register”