Datasheet

883
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
42.7.11 Write Protected Registers
To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “ADC Write Protect Mode Register” (ADC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status Register
(ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset by reading the ADC Write Protect Status Register (ADC_WPSR).
The protected registers are:
 “ADC Mode Register”
 “ADC Channel Sequence 1 Register”
 “ADC Channel Sequence 2 Register”
 “ADC Channel Enable Register”
 “ADC Channel Disable Register”
 “ADC Extended Mode Register”
 “ADC Compare Window Register”
 “ADC Analog Control Register”
 “ADC Touchscreen Mode Register”
 “ADC Trigger Register”