Datasheet

628
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
36.7.3.8 Peripheral Deselection without DMA
During a transfer of more than one data on a Chip Select without the DMA, the SPI_TDR is loaded by the processor,
the flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal shift register. When this flag is
detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the end of the current transfer
and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted
between the two transfers. But depending on the application software handling the SPI status register flags (by interrupt
or polling method) or servicing other interrupts or other tasks, the processor may not reload the SPI_TDR in time to keep
the chip select active (low). A null Delay Between Consecutive Transfer (DLYBCT) value in the SPI_CSR register, will
give even less time for the processor to reload the SPI_TDR. With some SPI slave peripherals, requiring the chip select
line to remain active (low) during a full set of transfers might lead to communication errors.
To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be programmed with the CSAAT
bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active)
until transfer to another chip select is required. Even if the SPI_TDR is not reloaded the chip select will remain active. To
have the chip select line to raise at the end of the transfer the Last transfer Bit (LASTXFER) in the SPI_MR register must
be set at 1 before writing the last data to transmit into the SPI_TDR.
36.7.3.9 Peripheral Deselection with DMAC
When the Direct Memory Access Controller is used, the chip select line will remain low during the whole transfer since
the TDRE flag is managed by the DMAC itself. The reloading of the SPI_TDR by the DMAC is done as soon as TDRE
flag is set to one. In this case the use of CSAAT bit might not be needed. However, it may happen that when other DMAC
channels connected to other peripherals are in use as well, the SPI DMAC might be delayed by another (DMAC with a
higher priority on the bus). Having DMAC buffers in slower memories like flash memory or SDRAM compared to fast
internal SRAM, may lengthen the reload time of the SPI_TDR by the DMAC as well. This means that the SPI_TDR might
not be reloaded in time to keep the chip select line low. In this case the chip select line may toggle between data transfer
and according to some SPI Slave devices, the communication might get lost. The use of the CSAAT bit might be needed.
When the CSAAT bit is set at 0, the NPCS does not rise in all cases between two transfers on the same peripheral.
During a transfer on a Chip Select, the flag TDRE rises as soon as the content of the SPI_TDR is transferred into the
internal shifter. When this flag is detected the SPI_TDR can be reloaded. If this reload occurs before the end of the
current transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not
de-asserted between the two transfers. This might lead to difficulties for interfacing with some serial peripherals requiring
the chip select to be de-asserted after each transfer. To facilitate interfacing with such devices, the Chip Select Register
can be programmed with the CSNAAT bit (Chip Select Not Active After Transfer) at 1. This allows to de-assert
systematically the chip select lines during a time DLYBCS. (The value of the CSNAAT bit is taken into account only if the
CSAAT bit is set at 0 for the same Chip Select).
Figure 36-10 shows different peripheral deselection cases and the effect of the CSAAT and CSNAAT bits.