Datasheet

619
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
36.6 Product Dependencies
36.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must
first program the PIO controllers to assign the SPI pins to their peripheral functions.
36.6.2 Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the SPI clock.
36.6.3 Interrupt
The SPI interface has an interrupt line connected to the Interrupt Controller. Handling the SPI interrupt requires
programming the interrupt controller before configuring the SPI.
36.6.4 Direct Memory Access Controller (DMAC)
The SPI interface can be used in conjunction with the DMAC in order to reduce processor overhead. For a full description
of the DMAC, refer to the corresponding section in the full datasheet.
Table 36-2. I/O Lines
Instance Signal I/O Line Peripheral
SPI0 SPI0_MISO PA11 A
SPI0 SPI0_MOSI PA12 A
SPI0 SPI0_NPCS0 PA14 A
SPI0 SPI0_NPCS1 PA7 B
SPI0 SPI0_NPCS2 PA1 B
SPI0 SPI0_NPCS3 PB3 B
SPI0 SPI0_SPCK PA13 A
SPI1 SPI1_MISO PA21 B
SPI1 SPI1_MOSI PA22 B
SPI1 SPI1_NPCS0 PA8 B
SPI1 SPI1_NPCS1 PA0 B
SPI1 SPI1_NPCS2 PA31 B
SPI1 SPI1_NPCS3 PA30 B
SPI1 SPI1_SPCK PA23 B
Table 36-3. Peripheral IDs
Instance ID
SPI0 13
SPI1 14