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Table Of Contents

Description
1. Features
2. Block Diagram
3. Signal Description
4. Package and Pinout
- 4.1 Mechanical Overview of the 217-ball BGA Package
- 4.2 Mechanical Overview of the 247-ball BGA Package
- 4.3 217-ball BGA Package Pinout
- 4.4 247-ball BGA Package Pinout
5. Power Considerations
- 5.1 Power Supplies
6. Memories
- 6.1 Memory Mapping
- 6.2 Embedded Memories
  - 6.2.1 Internal SRAM
  - 6.2.2 Internal ROM
- 6.3 External Memories Overview
7. System Controller
- 7.1 System Controller Mapping
- 7.2 System Controller Block DIagram
- 7.3 Chip Identification
- 7.4 Backup Section
8. Peripherals
- 8.1 Peripheral Mapping
- 8.2 Peripheral Identifiers
- 8.3 Peripheral Interrupts and Clock Control
  - 8.3.1 System Interrupt
  - 8.3.2 External Interrupts
- 8.4 Peripheral Signal Multiplexing on I/O Lines
  - 8.4.1 Reset State
  - 8.4.2 PIO Line Selection
- 8.5 Fuse Box Features
  - 8.5.1 Read
  - 8.5.2 Write
9. ARM926EJ-S Processor Overview
- 9.1 Description
- 9.2 Embedded Characteristics
- 9.3 Block Diagram
- 9.4 ARM9EJ-S Processor
- 9.5 CP15 Coprocessor
  - 9.5.1 CP15 Registers Access
- 9.6 Memory Management Unit (MMU)
- 9.7 Caches and Write Buffer
  - 9.7.1 Instruction Cache (ICache)
  - 9.7.2 Data Cache (DCache) and Write Buffer
- 9.8 Bus Interface Unit
10. Debug and Test
- 10.1 Description
- 10.2 Embedded Characteristics
- 10.3 Block Diagram
- 10.4 Application Examples
  - 10.4.1 Debug Environment
  - 10.4.2 Test Environment
- 10.5 Debug and Test Pin Description
- 10.6 Functional Description
11. Advanced Interrupt Controller (AIC)
- 11.1 Description
- 11.2 Embedded Characteristics
- 11.3 Block Diagram
- 11.4 Application Block Diagram
- 11.5 AIC Detailed Block Diagram
- 11.6 I/O Line Description
- 11.7 Product Dependencies
- 11.8 Functional Description
- 11.9 Write Protection Registers
- 11.10 Advanced Interrupt Controller (AIC) User Interface
12. Boot Strategies
- 12.1 SAM9CN12 only
- 12.2 SAM9CN11 and SAM9N12 only
13. Boot Sequence Controller (BSC)
- 13.1 Description
- 13.2 Embedded Characteristics
- 13.3 Product Dependencies
- 13.4 Boot Sequence Controller (BSC) Registers User Interface
  - 13.4.1 Boot Sequence Configuration Register
14. Reset Controller (RSTC)
- 14.1 Description
- 14.2 Embedded Characteristics
- 14.3 Block Diagram
- 14.4 Functional Description
- 14.5 Reset Controller (RSTC) User Interface
15. Real-time Clock (RTC)
- 15.1 Description
- 15.2 Embedded Characteristics
- 15.3 Block Diagram
- 15.4 Product Dependencies
  - 15.4.1 Power Management
  - 15.4.2 Interrupt
- 15.5 Functional Description
- 15.6 Real-time Clock (RTC) User Interface
16. Periodic Interval Timer (PIT)
- 16.1 Description
- 16.2 Embedded Characteristics
- 16.3 Block Diagram
- 16.4 Functional Description
- 16.5 Periodic Interval Timer (PIT) User Interface
17. Watchdog Timer (WDT)
- 17.1 Description
- 17.2 Embedded Characteristics
- 17.3 Block Diagram
- 17.4 Functional Description
- 17.5 Watchdog Timer (WDT) User Interface
18. Shutdown Controller (SHDWC)
- 18.1 Description
- 18.2 Embedded Characteristics
- 18.3 Block Diagram
- 18.4 I/O Lines Description
- 18.5 Product Dependencies
  - 18.5.1 Power Management
- 18.6 Functional Description
- 18.7 Shutdown Controller (SHDWC) User Interface
19. General-Purpose Backup Registers (GPBR)
- 19.1 Description
- 19.2 Embedded Characteristics
- 19.3 General Purpose Backup Registers (GPBR) User Interface
  - 19.3.1 General Purpose Backup Register x
20. Slow Clock Controller (SCKC)
- 20.1 Description
- 20.2 Embedded Characteristics
- 20.3 Block Diagram
- 20.4 Slow Clock Controller (SCKC) User Interface
  - 20.4.1 Slow Clock Configuration Register
21. Clock Generator
- 21.1 Description
- 21.2 Embedded Characteristics
- 21.3 Block Diagram
- 21.4 Slow Clock Selection
- 21.5 Main Clock
- 21.6 Divider and PLL Block
  - 21.6.1 Divider and Phase Lock Loop Programming
22. Power Management Controller (PMC)
- 22.1 Description
- 22.2 Embedded Characteristics
- 22.3 Block Diagram
- 22.4 Master Clock Controller
- 22.5 Processor Clock Controller
- 22.6 USB Device and Host Clocks
- 22.7 LP-DDR/DDR2 Clock
- 22.8 Peripheral Clock Controller
- 22.9 Programmable Clock Output Controller
- 22.10 Programming Sequence
- 22.11 Clock Switching Details
  - 22.11.1 Master Clock Switching Timings
  - 22.11.2 Clock Switching Waveforms
- 22.12 Power Management Controller (PMC) User Interface
23. Parallel Input/Output Controller (PIO)
- 23.1 Description
- 23.2 Embedded Characteristics
- 23.3 Block Diagram
- 23.4 Product Dependencies
- 23.5 Functional Description
- 23.6 I/O Lines Programming Example
- 23.7 Parallel Input/Output Controller (PIO) User Interface
24. Debug Unit (DBGU)
- 24.1 Description
- 24.2 Embedded Characteristics
- 24.3 Block Diagram
- 24.4 Product Dependencies
- 24.5 UART Operations
- 24.6 Debug Unit (DBGU) User Interface
25. Fuse Controller (FUSE)
- 25.1 Description
- 25.2 Embedded Characteristics
- 25.3 Block Diagram
- 25.4 Functional Description
- 25.5 Fuse Controller (FUSE) User Interface
26. Bus Matrix (MATRIX)
- 26.1 Description
- 26.2 Embedded Characteristics
- 26.3 Matrix Masters
- 26.4 Matrix Slaves
- 26.5 Master to Slave Access
- 26.6 Memory Mapping
- 26.7 Special Bus Granting Mechanism
- 26.8 Arbitration
  - 26.8.1 Arbitration Scheduling
    - 26.8.1.1 Undefined Length Burst Arbitration
    - 26.8.1.2 Slot Cycle Limit Arbitration
  - 26.8.2 Arbitration Priority Scheme
    - 26.8.2.1 Fixed Priority Arbitration
    - 26.8.2.2 Round-Robin Arbitration
- 26.9 Write Protect Registers
- 26.10 Bus Matrix (MATRIX) User Interface
27. External Bus Interface (EBI)
- 27.1 Description
- 27.2 Embedded Characteristics
- 27.3 EBI Block Diagram
- 27.4 I/O Lines Description
- 27.5 Application Example
  - 27.5.1 Hardware Interface
  - 27.5.2 Connection Examples
- 27.6 Product Dependencies
  - 27.6.1 I/O Lines
- 27.7 Functional Description
- 27.8 Implementation Examples
28. Programmable Multibit ECC Controller (PMECC)
- 28.1 Description
- 28.2 Embedded Characteristics
- 28.3 Block Diagram
- 28.4 Functional Description
  - 28.4.1 MLC/SLC Write Page Operation using PMECC
    - 28.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set
    - 28.4.1.2 MLC/SLC Write Operation with Spare Area Disabled
  - 28.4.2 MLC/SLC Read Page Operation using PMECC
- 28.5 Software Implementation
- 28.6 Programmable Multibit ECC Controller (PMECC) User Interface
29. Programmable Multibit ECC Error Location Controller (PMERRLOC)
- 29.1 Description
- 29.2 Embedded Characteristics
- 29.3 Block Diagram
- 29.4 Functional Description
- 29.5 Programmable Multibit ECC Error Location (PMERRLOC) User Interface
30. Static Memory Controller (SMC)
- 30.1 Description
- 30.2 Embedded Characteristics
- 30.3 I/O Lines Description
- 30.4 Multiplexed Signals
- 30.5 Application Example
  - 30.5.1 Hardware Interface
- 30.6 Product Dependencies
  - 30.6.1 I/O Lines
- 30.7 External Memory Mapping
- 30.8 Connection to External Devices
  - 30.8.1 Data Bus Width
  - 30.8.2 Byte Write or Byte Select Access
- 30.9 Standard Read and Write Protocols
- 30.10 Automatic Wait States
- 30.11 Data Float Wait States
- 30.12 External Wait
- 30.13 Slow Clock Mode
  - 30.13.1 Slow Clock Mode Waveforms
  - 30.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode
- 30.14 Asynchronous Page Mode
- 30.15 Programmable IO Delays
- 30.16 Static Memory Controller (SMC) User Interface
31. DDR SDR SDRAM Controller (DDRSDRC)
- 31.1 Description
- 31.2 Embedded Characteristics
- 31.3 DDRSDRC Module Diagram
- 31.4 Initialization Sequence
- 31.5 Functional Description
- 31.6 Software Interface/SDRAM Organization, Address Mapping
- 31.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface
32. DMA Controller (DMAC)
- 32.1 Description
- 32.2 Embedded Characteristics
- 32.3 DMA Controller Peripheral Connections
- 32.4 Block Diagram
- 32.5 Functional Description
- 32.6 DMAC Software Requirements
- 32.7 Write Protection Registers
- 32.8 DMA Controller (DMAC) User Interface
33. USB Device Port (UDP)
- 33.1 Description
- 33.2 Embedded Characteristics
- 33.3 Block Diagram
  - 33.3.1 Signal Description
- 33.4 Product Dependencies
- 33.5 Typical Connection
  - 33.5.1 USB Device Transceiver
  - 33.5.2 VBUS Monitoring
- 33.6 Functional Description
- 33.7 USB Device Port (UDP) User Interface
34. USB Host Port (UHP)
- 34.1 Description
- 34.2 Embedded Characteristics
- 34.3 Block Diagram
- 34.4 Product Dependencies
- 34.5 Functional Description
  - 34.5.1 Host Controller Interface
  - 34.5.2 Host Controller Driver
- 34.6 Typical Connection
35. High Speed MultiMedia Card Interface (HSMCI)
- 35.1 Description
- 35.2 Embedded Characteristics
- 35.3 Block Diagram
- 35.4 Application Block Diagram
- 35.5 Pin Name List
- 35.6 Product Dependencies
- 35.7 Bus Topology
- 35.8 High Speed MultiMedia Card Operations
- 35.9 SD/SDIO Card Operation
  - 35.9.1 SDIO Data Transfer Type
  - 35.9.2 SDIO Interrupts
- 35.10 CE-ATA Operation
- 35.11 HSMCI Boot Operation Mode
  - 35.11.1 Boot Procedure, Processor Mode
  - 35.11.2 Boot Procedure DMA Mode
- 35.12 HSMCI Transfer Done Timings
- 35.13 Register Write Protection
- 35.14 High Speed MultiMedia Card Interface (HSMCI) User Interface
36. Serial Peripheral Interface (SPI)
- 36.1 Description
- 36.2 Embedded Characteristics
- 36.3 Block Diagram
- 36.4 Application Block Diagram
- 36.5 Signal Description
- 36.6 Product Dependencies
- 36.7 Functional Description
- 36.8 Serial Peripheral Interface (SPI) User Interface
37. Timer Counter (TC)
- 37.1 Description
- 37.2 Embedded Characteristics
- 37.3 Block Diagram
- 37.4 Pin Name List
- 37.5 Product Dependencies
- 37.6 Functional Description
- 37.7 Timer Counter (TC) User Interface
38. Pulse Width Modulation Controller (PWM)
- 38.1 Description
- 38.2 Embedded characteristics
- 38.3 Block Diagram
- 38.4 I/O Lines Description
- 38.5 Product Dependencies
- 38.6 Functional Description
- 38.7 Pulse Width Modulation Controller (PWM) User Interface
39. Two-wire Interface (TWI)
- 39.1 Description
- 39.2 Embedded Characteristics
- 39.3 List of Abbreviations
- 39.4 Block Diagram
- 39.5 Application Block Diagram
  - 39.5.1 I/O Lines Description
- 39.6 Product Dependencies
- 39.7 Functional Description
  - 39.7.1 Transfer Format
  - 39.7.2 Modes of Operation
- 39.8 Master Mode
- 39.9 Multi-master Mode
  - 39.9.1 Definition
  - 39.9.2 Different Multi-master Modes
    - 39.9.2.1 TWI as Master Only
    - 39.9.2.2 TWI as Master or Slave
- 39.10 Slave Mode
- 39.11 Write Protection System
- 39.12 Two-wire Interface (TWI) User Interface
40. Universal Synchronous Asynchronous Receiver Transceiver (USART)
- 40.1 Description
- 40.2 Embedded Characteristics
- 40.3 Block Diagram
- 40.4 Application Block Diagram
- 40.5 I/O Lines Description
- 40.6 Product Dependencies
- 40.7 Functional Description
- 40.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface
41. Universal Asynchronous Receiver Transmitter (UART)
- 41.1 Description
- 41.2 Embedded Characteristics
- 41.3 Block Diagram
- 41.4 Product Dependencies
- 41.5 UART Operations
- 41.6 Universal Asynchronous Receiver Transmitter (UART) User Interface
42. Analog-to-Digital Converter (ADC)
- 42.1 Description
- 42.2 Embedded Characteristics
- 42.3 Block Diagram
- 42.4 Signal Description
- 42.5 Product Dependencies
- 42.6 Functional Description
- 42.7 Touchscreen
- 42.8 Analog-to-Digital Converter (ADC) User Interface
43. Synchronous Serial Controller (SSC)
- 43.1 Description
- 43.2 Embedded Characteristics
- 43.3 Block Diagram
- 43.4 Application Block Diagram
- 43.5 Pin Name List
- 43.6 Product Dependencies
- 43.7 Functional Description
- 43.8 SSC Application Examples
  - 43.8.1 Write Protection Registers
- 43.9 Synchronous Serial Controller (SSC) User Interface
44. LCD Controller (LCDC)
- 44.1 Description
- 44.2 Embedded Characteristics
- 44.3 Block Diagram
- 44.4 I/O Lines Description
- 44.5 Product Dependencies
- 44.6 Functional Description
- 44.7 LCD Controller (LCDC) User Interface
45. Advanced Encryption Standard (AES)
- 45.1 Description
- 45.2 Embedded Characteristics
- 45.3 Product Dependencies
  - 45.3.1 Power Management
  - 45.3.2 Interrupt
- 45.4 Functional Description
- 45.5 Security Features
  - 45.5.1 Unspecified Register Access Detection
- 45.6 Advanced Encryption Standard (AES) User Interface
46. Secure Hash Algorithm (SHA)
- 46.1 Description
- 46.2 Embedded Characteristics
- 46.3 Product Dependencies
  - 46.3.1 Power Management
  - 46.3.2 Interrupt
- 46.4 Functional Description
- 46.5 Secure Hash Algorithm (SHA) User Interface
47. True Random Number Generator (TRNG)
- 47.1 Description
- 47.2 Embedded Characteristics
- 47.3 Block Diagram
- 47.4 Product Dependencies
  - 47.4.1 Power Management
  - 47.4.2 Interrupt
- 47.5 Functional Description
- 47.6 True Random Number Generator (TRNG) User Interface
48. Electrical Characteristics
- 48.1 Absolute Maximum Ratings
- 48.2 DC Characteristics
- 48.3 Power Consumption
  - 48.3.1 Power Consumption versus Modes
- 48.4 Clock Characteristics
- 48.5 12 MHz RC Oscillator Characteristics
- 48.6 32 kHz Oscillator Characteristics
  - 48.6.1 32 kHz Crystal Characteristics
  - 48.6.2 XIN32 Clock Characteristics
- 48.7 32 kHz RC Oscillator Characteristics
- 48.8 PLL Characteristics
- 48.9 I/Os
- 48.10 Analog-to-Digital Converter (ADC)
- 48.11 USB Transceiver Characteristics
  - 48.11.1 Electrical Characteristics
- 48.12 Core Power Supply POR Characteristics
  - 48.12.1 Power Sequence Requirements
  - 48.12.2 Power-Up Sequence
- 48.13 SMC Timings
  - 48.13.1 Timing Conditions
  - 48.13.2 Timing Extraction
- 48.14 DDRSDRC Timings
- 48.15 Peripheral Timings
49. Mechanical Overview of the 217-ball and 247-ball BGA Packages
- 49.1 217-ball BGA Package
- 49.2 247-ball BGA Package
- 49.3 Marking
50. SAM9N12/SAM9CN11/SAM9CN12 Ordering Information
51. SAM9N/CN Series Errata
- 51.1 SAM9N12/CN11/CN12 Errata
- 51.2 SAM9CN12 Errata: Revision A
  - 51.2.1 BootROM
    - 51.2.1.1 Boot from SPI Serial Flash Devices (xx25xxx) Is not Working
  - 51.2.2 16 MHz Main Crystal
    - 51.2.2.1 16 MHz Main Crystal Detection
- 51.3 SAM9CN12 Errata: Revision B
  - 51.3.1 Boot ROM
    - 51.3.1.1 Boot from SPI Data/Serial Flash Devices do not work with All Memories
Revision History
Table of Contents

553

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

• EPEDS: Endpoint Enable Disable

Read:

0 = Endpoint disabled.

1 = Endpoint enabled.

Write:

0 = Disables endpoint.

1 = Enables endpoint.

Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints.

Note: After reset, all endpoints are configured as control endpoints (zero).

• RXBYTECNT[10:0]: Number of Bytes Available in the FIFO

Read-only

When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The

microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx register.