Datasheet

497
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
32.8.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register
Name: DMAC_EBCIDR
Address: 0xFFFFEC1C
Access: Write-only
Reset: 0x00000000
• BTCx: Buffer Transfer Completed [7:0]
Buffer transfer completed Disable Interrupt Register. When set, a bit of the BTC field disables the interrupt from the relevant
DMAC channel.
• CBTCx: Chained Buffer Transfer Completed [7:0]
Chained Buffer transfer completed Disable Register. When set, a bit of the CBTC field disables the interrupt from the relevant
DMAC channel.
• ERRx: Access Error [7:0]
Access Error Interrupt Disable Register. When set, a bit of the ERR field disables the interrupt from the relevant DMAC channel.
• DICERRx: Descriptor Integrity Check Error [7:0]
Descriptor Integrity Check Error Interrupt Disable Register, When set, a bit of the DICERR field disables the interrupt from the rel-
evant DMAC channel.
31 30 29 28 27 26 25 24
DICERR7 DICERR6 DICERR5 DICERR4 DICERR3 DICERR2 DICERR1 DICERR0
23 22 21 20 19 18 17 16
ERR7 ERR6 ERR5 ERR4 ERR3 ERR2 ERR1 ERR0
15 14 13 12 11 10 9 8
CBTC7 CBTC6 CBTC5 CBTC4 CBTC3 CBTC2 CBTC1 CBTC0
76543210
BTC7 BTC6 BTC5 BTC4 BTC3 BTC2 BTC1 BTC0