Datasheet

496
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
32.8.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register
Name: DMAC_EBCIER
Address: 0xFFFFEC18
Access: Write-only
Reset: 0x00000000
• BTCx: Buffer Transfer Completed [7:0]
Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the BTC field to enable the interrupt for channel i.
• CBTCx: Chained Buffer Transfer Completed [7:0]
Chained Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the CBTC field to enable the interrupt for
channel i.
• ERRx: Access Error [7:0]
Access Error Interrupt Enable Register. Set the relevant bit in the ERR field to enable the interrupt for channel i.
• DICERRx: Descriptor Integrity Check Error [7:0]
Descriptor Integrity Check Error Interrupt Enable Register. Set the relevant bit in the DICERR field to enable the interrupt for
channel i.
31 30 29 28 27 26 25 24
DICERR7 DICERR6 DICERR5 DICERR4 DICERR3 DICERR2 DICERR1 DICERR0
23 22 21 20 19 18 17 16
ERR7 ERR6 ERR5 ERR4 ERR3 ERR2 ERR1 ERR0
15 14 13 12 11 10 9 8
CBTC7 CBTC6 CBTC5 CBTC4 CBTC3 CBTC2 CBTC1 CBTC0
76543210
BTC7 BTC6 BTC5 BTC4 BTC3 BTC2 BTC1 BTC0