Datasheet

479
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
18. The DMAC reloads the DMAC_SADDRx register from the initial value. The hardware sets the Buffer Transfer
Completed Interrupt. The DMAC samples the row number as shown in Table 32-2 on page 469. If the DMAC is in
Row 1, then the DMAC transfer has completed. The hardware sets the Chained Buffer Transfer Completed Inter-
rupt and disables the channel. You can either respond to the Buffer Transfer Completed Interrupt or Chained
Buffer Transfer Completed Interrupt, or poll for the Channel Enable. (DMAC_CHSR.ENAx) bit until it is cleared by
hardware, to detect when the transfer is complete. If the DMAC is not in Row 1 as shown in Table 32-2 on page
469, the following step is performed.
19. The DMAC fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, and
automatically reprograms the DMAC_DADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel
registers. Note that the DMAC_SADDRx is not re-programmed as the reloaded value is used for the next DMAC
buffer transfer. If the next buffer is the last buffer of the DMAC transfer, then the DMAC_CTRLBx and
DMAC_DSCRx registers just fetched from the LLI should match Row 1 of Table 32-2 on page 469. The DMAC
transfer might look like that shown in Figure 32-12 on page 479.
Figure 32-12. Multi-buffer DMAC Transfer with Source Address Auto-reloaded and Linked List Destination Address
The DMAC Transfer flow is shown in Figure 32-13 on page 480.
Address of
Source Layer
Address of
Destination Layer
Source Buffers
Destination Buffers
SADDR
Buffer0
Buffer1
Buffer2
BufferN
DADDR(N)
DADDR(1)
DADDR(0)
DADDR(2)