Datasheet

461
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
32.3 DMA Controller Peripheral Connections
The DMA Controller handles the transfer between peripherals and memory and receives triggers from the peripherals
listed in table that follows.
For each listed DMA Channel Number, the SIF and/or DIF bitfields in the DMAC_CTRLBx register must be programmed
with a value compatible to the MATRIX “Master to Slave Access” definition provided in the “Bus Matrix (MATRIX)” section
of the product datasheet. See Section 32.8.17 ”DMAC Channel x [x = 0..7] Control B Register” (where x is the DMA
Channel Number).
Depending on transfer descriptor location, the DSCR_IF bitfield must be programmed with a value compatible to the
MATRIX “Master to Slave Access” definition provided in the “Bus Matrix (MATRIX)” section of the product datasheet.
See Section 32.8.15 ”DMAC Channel x [x = 0..7] Descriptor Address Register” (where x is the DMA Channel Number).
Table 32-1. DMA Channel Definition
Instance Name Channel T/R DMA Channel HW Interface Number
HSMCI RX/TX 0
SPI0 TX 1
SPI0 RX 2
SPI1 TX 3
SPI1 RX 4
USART0 TX 5
USART0 RX 6
USART1 TX 7
USART1 RX 8
USART2 TX 9
USART2 RX 10
USART3 TX 11
USART3 RX 12
TWI0 TX 13
TWI0 RX 14
TWI1 TX 15
TWI1 RX 16
UART0 TX 17
UART0 RX 18
UART1 TX 19
UART1 RX 20
SSC TX 21
SSC RX 22
ADC RX 23
DBGU TX 24
DBGU RX 25
AES TX 26
AES RX 27
SHA TX 28