Datasheet

451
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
31.7.5 DDRSDRC Timing Parameter 1 Register
Name: DDRSDRC_TPR1
Address: 0xFFFFE810
Access: Read-write
Reset: See Table 31-16
This register can only be written if the WPEN bit is cleared in “DDRSDRC Write Protect Mode Register” .
• TRFC: Row Cycle Delay
Reset Value is 8 cycles.
This field defines the delay between a Refresh and an Activate command or Refresh command in number of cycles. Number of
cycles is between 0 and 31
• TXSNR: Exit Self-refresh Delay to Non-read Command
Reset Value is 8 cycles.
This field defines the delay between cke set high and a non Read Command in number of cycles. Number of cycles is between 0
and 255. This field is used for SDR-SDRAM and DDR-SDRAM devices. In the case of SDR-SDRAM devices and Low-power
DDR1-SDRAM, this field is equivalent to TXSR timing.
• TXSRD: ExiT Self-refresh Delay to Read Command
Reset Value is 200 cycles.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between 0 and
255 cycles.This field is unique to DDR-SDRAM devices. In the case of a Low-power DDR1-SDRAM, this field must be written to 0.
• TXP: Exit Power-down Delay to First Command
Reset Value is 3 cycles.
This field defines the delay between cke set high and a Valid Command in number of cycles. Number of cycles is between 0 and
15 cycles. This field is unique to Low-power DDR1-SDRAM devices and DDR2-SDRAM devices.
31 30 29 28 27 26 25 24
–––– TXP
23 22 21 20 19 18 17 16
TXSRD
15 14 13 12 11 10 9 8
TXSNR
76543210
––– TRFC