Datasheet

Table Of Contents
450
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
TWTR: Internal Write to Read Delay
Reset value is 0.
This field is relevant only for Low-power DDR1-SDRAM devices and DDR2-SDRAM devices.
This field defines the internal write to read command Time in number of cycles. Number of cycles is between 1 and 7.
In the case of low-power DDR1-SDRAM device the coding is different
REDUCE_WRRD: Reduce Write to Read Delay
Reset value is 0.
This field reduces the delay between write to read access for low-power DDR-SDRAM devices with a latency equal to 2. To use
this feature, TWTR field must be equal to 0. Important to note is that some devices do not support this feature.
•TMRD: Load Mode Register Command to Active or Refresh Command
Reset Value is 2 cycles.
This field defines the delay between a Load mode register command and an active or refresh command in number of cycles.
Number of cycles is between 0 and 15.
Value Name Description
1 ONE 1 SDCK clock cycle delay
2 TWO 2 SDCK clock cycle delay
3 THREE 3 SDCK clock cycle delay
4 FOUR 4 SDCK clock cycle delay
5 FIVE 5 SDCK clock cycle delay
6 SIX 6 SDCK clock cycle delay
7 SEVEN 7 SDCK clock cycle delay
Value Name Description
0 ONE Does 1
1 TWO Does 2