Datasheet

435
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 31-22. Power-down Entry/Exit, Timeout = 0
31.5.4.3 Deep Power-down Mode
The deep power-down mode is a new feature of the Low-power SDRAM. When this mode is activated, all internal voltage
generators inside the device are stopped and all data is lost.
This mode is activated by setting the low-power command bit (LPCB) to ‘3’ in “DDRSDRC Low-power Register” . When
this mode is enabled, the DDRSDRC leaves normal mode (mode = 0) and the controller is frozen. To exit deep power-
down mode, the low-power bits (LPCB) must be set to ‘0’, an initialization sequence must be generated by software. See
Section 31.4.2 “Low-power DDR1-SDRAM Initialization” on page 419.
Figure 31-23. Deep Power-down Mode Entry
Entry power down mode
Exit power down mode
SDCLK
A[12:0]
READ BST NOP READ
COMMAND
CKE
0
BA[1:0]
DQS[1:0]
Da Db
D[15:0]
3
DM[1:0]
NOP READ BST NOP PRCHG NOP DEEPOWER NOP
0
Trp
Enter Deep
Power-down
Mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[1:0]
Da Db
D[15:0]
3
DM[1:0]