Datasheet

223
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Notes: 1. Reset value depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the
PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was
disabled.
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
occurred.
5. If an offset is not listed in the table it must be considered as reserved.
0x008C Slow Clock Divider Debouncing Register PIO_SCDR Read/Write 0x00000000
0x0090 Pad Pull-down Disable Register PIO_PPDDR Write-only –
0x0094 Pad Pull-down Enable Register PIO_PPDER Write-only –
0x0098 Pad Pull-down Status Register PIO_PPDSR Read-only
(1)
0x009C Reserved – – –
0x00A0 Output Write Enable PIO_OWER Write-only –
0x00A4 Output Write Disable PIO_OWDR Write-only –
0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000
0x00AC Reserved – – –
0x00B0 Additional Interrupt Modes Enable Register PIO_AIMER Write-only –
0x00B4 Additional Interrupt Modes Disable Register PIO_AIMDR Write-only –
0x00B8 Additional Interrupt Modes Mask Register PIO_AIMMR Read-only 0x00000000
0x00BC Reserved – – –
0x00C0 Edge Select Register PIO_ESR Write-only –
0x00C4 Level Select Register PIO_LSR Write-only –
0x00C8 Edge/Level Status Register PIO_ELSR Read-only 0x00000000
0x00CC Reserved – – –
0x00D0 Falling Edge/Low-Level Select Register PIO_FELLSR Write-only –
0x00D4 Rising Edge/ High-Level Select Register PIO_REHLSR Write-only –
0x00D8 Fall/Rise - Low/High Status Register PIO_FRLHSR Read-only 0x00000000
0x00DC Reserved – – –
0x00E0 Reserved – – –
0x00E4 Write Protection Mode Register PIO_WPMR Read/Write 0x0
0x00E8 Write Protection Status Register PIO_WPSR Read-only 0x0
0x00EC
to
0x00F8
Reserved – – –
0x0100 Schmitt Trigger Register PIO_SCHMITT Read/Write 0x00000000
0x0104-
0x010C
Reserved – – –
0x0110 IO Delay Register PIO_DELAYR Read/Write 0x00000000
0x0114 I/O Drive Register 1 PIO_DRIVER1 Read/Write 0x00000000
0x0118 I/O Drive Register 2 PIO_DRIVER2 Read/Write 0x00000000
0x011C Reserved – – –
0x0120
to
0x014C
Reserved – – –
Table 23-2. Register Mapping (Continued)
Offset Register Name Access Reset