Datasheet

196
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
22.12.10 PMC Clock Generator PLLB Register
Name: CKGR_PLLBR
Address: 0xFFFFFC2C
Access: Read-write
Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
• DIVB: Divider B
0: Divider output is 0.
1: Divider is bypassed.
2 up to 255 = Divider output is the selected clock divided by DIVB
• PLLBCOUNT: PLLB Counter
Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• OUTB: PLLB Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Characteris-
tics section of the product datasheet.
• MULB: PLLB Multiplier
0 : The PLLB is deactivated.
1 up to 254: The PLLB Clock frequency is the PLLB input frequency multiplied by MULB+1.
31 30 29 28 27 26 25 24
––––– MULB
23 22 21 20 19 18 17 16
MULB
15 14 13 12 11 10 9 8
OUTB PLLBCOUNT
76543210
DIVB