Datasheet

195
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
22.12.9 PMC Clock Generator PLLA Register
Name: CKGR_PLLAR
Address: 0xFFFFFC28
Access: Read-write
Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC.
Warning:
Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
• DIVA: Divider A
0: Divider output is 0.
1: Divider is bypassed.
2 up to 255: Divider output is the selected clock divided by DIVA
• PLLACOUNT: PLLA Counter
Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• OUTA: PLLA Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Characteris-
tics section of the product datasheet.
• MULA: PLLA Multiplier
0: The PLLA is deactivated.
1 up to 254: The PLLA Clock frequency is the PLLA input frequency multiplied by MULA+ 1.
31 30 29 28 27 26 25 24
––1–– MULA
23 22 21 20 19 18 17 16
MULA
15 14 13 12 11 10 9 8
OUTA PLLACOUNT
76543210
DIVA