Datasheet

1093
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
HSMCI:
Table 35-8, “Register Mapping” and Section 35.14.20 “HSMCI FIFOx Memory Aperture”, HSMCI_FIFOx offset
updated.
7253
MATRIX:
Section 26-5 “Chip Configuration User Interface”, CCFG_EBICSA offset values revised. rfo
PIO:
Figure 23-3, I/O Line Control Logic, Table 23-2, “Register Mapping”, “PIO Input Filter Slow Clock Disable
Register”, “PIO Input Filter Slow Clock Enable Register”, “PIO Input Filter Slow Clock Status
Register”,updated IFSxx register acronyms.
Table 23-2, “Register Mapping”, “PIO I/O Drive Register 1” and “PIO I/O Drive Register 2” added to datasheet.
6787
6876, 7255
PMC:
Section 22.12 “Power Management Controller (PMC) User Interface”, PLLB is usable as input clock.
Section 22-3 “Register Mapping”, offset 0x0038 updated with USB Clock Register (PMC_USB).
Section 22.5 “Processor Clock Controller”, revised.
Section 22.12.10 “PMC Clock Generator PLLB Register”, removed USBDIV bitfields.
Section 22.12.12 “USB Clock Register”, added to datasheet.
7304
rfo
7369
rfo
PMEEC:
ERRIE, ERRID, ERRIM bitfields are 1 bit wide. See:Section 28.6.8 “PMECC Interrupt Enable Register”,
Section 28.6.9 “PMECC Interrupt Disable Register” and Section 28.6.10 “PMECC Interrupt Mask Register”.
7202
PMERRLOC:
Table 29-3, “Register Mapping” PMECC SIGMA 24 is located at 0x088.
Section 29.5.10 “Error Location SIGMAx Register”, updated.
7203
SCKC:
Section 20. “Slow Clock Controller (SCKC)”, added to datasheet. rfo
SMC:
Table 30-1, “I/O Line Description”, replaced NCS[7:0] by NCS[5:0] rfo
SPI:
Section 36.8.9 “SPI Chip Select Register”, “SCBR: Serial Clock Baud Rate”, data transfer note added.
Section 36.8.3 “SPI Receive Data Register”added requirements to bitfield “PCS: Peripheral Chip Select”.
Section 36.8.9 “SPI Chip Select Register”, “BITS: Bits Per Transfer”, bitfield table; Description column revised.
Section 36.7.3.5 “Peripheral Selection”, added paragraph at end of the section.
7247
7319
7267
TC:
Section 37.7.5 “TC Channel Mode Register: Waveform Mode”, updated WAVSEL bitfield table.
“TC Counter Value Register”, “TC Register A”, “TC Register B”, “TC Register C” all bitfields are filled.
Figure 37-5, Capture Mode a
nd Fi
gure 37-6, Waveform Mode, revise the counter component.
7190
7318
TRNG:
Section 47.2 “Embedded Characteristics”, removed 133 MHz Clock Frequency.
Section 47.3.1 “TRNG Control Register”, added KEY bitfield.
rfo
5914
TWI:
Section 39.8.7 “Using the DMA Controller”, added to the datasheet. 7306
Doc. Rev
11063C
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