Datasheet

1092
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Doc. Rev
11063C
Comments Change
Request
Ref.
Overview:
“Description” SLC NAND Flash is supported.
Section “Description”, 1st paragraph, the 2nd sentence was removed.
Table 4-1, “BGA217 Pin Description”, table updated with values in Ball column.
Table 5-1, “SAM9N12/CN11/CN12 Power Supplies”, VDDFUSE Voltage Range updated, 3.0V-3.6V.
Section 6.3.3 “DDR-SDRAM Controller”, revised.
Section 7.3 “Chip Identification”, removed “two” lines.
Section 8.4 “Peripheral Signal Multiplexing on I/O Lines”, removed irrelevant text.
Elsewhere, minor grammar revisions. Advance Information status moved to Preliminary.
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ARM Processor:
Section 9. “ARM926EJ-S Processor Overview”, removed Tightly-Coupled Memory Interface chapter.
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Debug and Test:
Figure 10-1, Debug and Test Block Diagram, removed PDC. rfo
Boot Program:
Figure 12-1, ROM Code Algorithm Flow Diagram, updated.
Section 12.2 “SAM9CN11 and SAM9N12 only”, and forward, grammar and format edits.
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ADC:
Section 42.8.12 “ADC Interrupt Status Register”, fixed ADC_SR typos to ADC_ISR.
Section 42.8.14 “ADC Extended Mode Register”, values 2 and 3 swapped in CMPMODE bitfield table.
Section 42.8.16 “ADC Channel Data Register”, DATA bitfield extended to fields 11 and 10.
Section 42.6.5 “Conversion Triggers”, TRGMOD bitfield refers to Section 42.8.22 “ADC Trigger Register”.
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AES:
Section 45.5.1 “Unspecified Register Access Detection”, updated. 7357
AIC:
Section 11.9 “Write Protection Registers” added to datasheet.
“SRCTYPE: Interrupt Source Type” on page 68 bitfield description table updated.
“PRIOR: Priority Level” on page 68, bitfield described in a table.
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DDRSDRC:
Section 31.2 “Embedded Characteristics”,removed... “eight internal banks not supported.”
Section 31.5.4.1 “Self-refresh Mode” UDP_EN replaced by UPD_MR. In Section 31.7.7 “DDRSDRC Low-
power Register” UDP_MR typo corrected.
“TWTR: Internal Write to Read Delay”, bitfield table updated.
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DMAC:
“FC: Flow Control”, removed last four lines from bitfield table.
Section 32.5.1 “Basic Definitions”, added Programmable Arbitration Policy.
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External Memories:
Section 27.8.7 “8-bit NAND Flash with NFD0_ON_D16 = 1”
Section 27.8.7.2 “Software Configuration”, added the line: “Configure the PIOD controller to assign...”
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