Datasheet

1090
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Doc. Rev
11063F
Comments Change
Request
Ref.
Description:
Section “Description”, 125 MHz --> 133 MHz
“FIPS PUB 46-3 compliant TDES” removed from 3rd paragraph
7928
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Signal Description:
Table 3-1, “Signal Description List”, NFD0-NFD16 --> NFD0-NFD15
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Power Considerations:
Section 5.2 Programmable I/O Lines Power Supplies and Current Drive removed from Section 5. “Power
Considerations”, as the same contents already exists in Section 27.7.4 “Power Supplies”
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System Controller:
Section 7.3 “Chip Identification”, Chip ID: 0x819A_07A0 --> 0x819A_07A1
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Peripherals:
Table 8-1, “SAM9N12/CN11/CN12 Peripheral Identifiers”:Replaced keyword ‘Reserved’ on 4th row with
‘FUSE’
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EBI:
Section 27.7.4 “Power Supplies”, following sentences added before the 2nd figure: “This can be used if
the SMC connects to the NAND Flash only. Using this function with another device on the SMC will
lead to an unpredictable behavior of that device. In that case, a default value must be selected.”
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FUSE:
Section 25. “Fuse Controller (FUSE)” added.
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MATRIX:
Section 26.10.5.1 “EBI Chip Select Assignment Register”, NFD0_ON_D16 bitfield description updated
8008
PMC:
Section 21.2 “Embedded Characteristics”, 266 MHz DDR --> 133 MHz DDR
Section 22.8 “Peripheral Clock Controller”, PMC_PCR, 0x10030102 --> PMC_PCR,0x10031002
7975
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Electrical Characteristics:
Table 48-5, “Processor Clock Waveform Parameters” and Table 48-6, “System Clock Waveform
Parameters”, ‘Corner MAX’ changed to ‘VVDDCORE min’ and second row removed. In the note below,
‘LDDDR’ changed to ‘LPDDR’
Table 48-9, “XIN Clock Electrical Characteristics”, VIN row split into 2 rows: V
XINLOW
and V
XINHIGH
Section 48.13 “SMC Timings”, “SMC Timings are given for MAX corners” removed
Table 48-18, “Channel Conversion Time and ADC Clock” : ‘ADC Clock = 5 MHz’ row added to Conversion
Time (TCT) and to ‘Throughput Rate’
Table 48-21, “Transfer Characteristics”, 2 rows added: ‘ADC Clock = 13.2 MHz’ and ‘ADC Clock = 5 MHz’
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8009
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7947