Datasheet

1089
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Doc. Rev
11063G
Comments Change
Request
Ref.
Overview:
Added “Write Protected Registers in Section 1. “Features”.
Product name updated to SAM9N12/SAM9CN11/SAM9CN12.
“Description” updated with the various devices configurations.
Bullets for SAM9CN11 and SAM9N12 added in Section 7.3 “Chip Identification”.
8213
8244
Boot Strategies:
Boot Strategy from SAM9CN12 removed to create the separate Secure Boot document, and replaced by the
previous Boot Strategies from SAM9N12.
Table 12-1, “External Clock and Crystal frequencies allowed for Boot Sequence (in MHz)” added in Section
12.2.3 “Chip Setup”.
8202
8270
RSTC:
RSTC conditions improved. 8083
HSMCI:
Sentence "This flag must be used only for Write Operations” removed in “NOTBUSY: HSMCI Not Busy” on
page 602.
8394
USART:
Whole chapter updated. rfo
SSC:
Reworked tables and bitfield descriptions in Section 43.9.3 “SSC Receive Clock Mode Register”, Section
43.9.4 “SSC Receive Frame Mode Register”, Section 43.9.5 “SSC Transmit Clock Mode Register”, Section
43.9.6 “SSC Transmit Frame Mode Register”. Replaced AIC/NVIC wording with “interrupt controller”.
8466
AES:
Hardware Counter Measures updated in Section 45.2 ”Embedded Characteristics” and in Section 45.5.1
”Unspecified Register Access Detection”.
rfo
SHA:
Mode Register reset value updated to 0x1 in Table 46-2, “Register Mapping”.rfo
Ordering Information:
Ordering codes added for SAM9N12 and SAM9CN11. 8244
Errata:
Errata created. Section 49.3 “Marking” moved to Section 51.1 “SAM9N12/CN11/CN12 Errata” on page
1077.
rfo
Back page:
Date updated. rfo