Datasheet

Table Of Contents
1085
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Section 39.11 ”Write Protection System”:
- replaced the acronym of the TWI Write Protection Status register with a cross-reference to the
corresponding section (the acronym changed: TWI_WPROT_STATUS --> TWI_WPSR)
- renamed bitfields of the write protection registers (WPROTERR --> WPVSRC, WPROTADDR -->
WPVSRC, SECURITY_CODE --> WPKEY)
Section 39.12 ”Two-wire Interface (TWI) User Interface”:
- Table 39-7 ”Register Mapping, added an offset for reserved registers (0x38-0xE0).
- Section 39.12.5 ”TWI Clock Waveform Generator Register”, fixed typos.
- Section 39.12.6 ”TWI Status Register”, replaced the description of ”NACK: Not Acknowledged (clear on
read)”, used in master mode, with a new text (value “1”, address byte is now referenced too)
- Section 39.12.11 ”TWI Transmit Holding Register”, changed the register access to Write-only
- Section 39.12.12 ”TWI Write Protection Mode Register”
- changed the register acronym: TWI_WPROT_MODE --> TWI_WPMR
- renamed bitfields:
WPROT --> WPEN, SECURITY_CODE --> WPKEY
- WPROT/WPEN: added details on Disable/Enable conditions and the list of protected registers
-
SECURITY_CODE/WPKEY: replaced the bit description with a table
- Section 39.12.13 ”TWI Write Protection Status Register”
- change the register acronym:
TWI_WPROT_STATUS --> TWI_WPSR
- renamed bitfields: WPROTERR --> WPVSRC, WPROTADDR --> WPVSRC
- updated entirely the description of bitfields
8845
8814
9145
9050
9050
9050
USART:
Section 40.3 ”Block Diagram” and Section 40.7.7 ”SPI Mode”:
- moved Table 40-1. SPI Operating Modes to Section 40.7.7.1 ”Modes of Operation” (now Table 40-13 ”SPI
Operating Mode”)
Section 40.7.1 ”Baud Rate Generator”, replaced “or 6” with “or 6 times lower” in the last phrase of the
introduction text.
Section 40.7.3.8 ”Parity”, corrected Figure 40-22, "Parity Error" for stop bit value.
Section 40.7.3.10 ”Transmitter Timeguard”, updated the Baud Rate value from “33,400” to “38,400” in Table
40-9 ”Maximum Timeguard Length Depending on Baud Rate”.
Section 40.7.3.11 ”Receiver Time-out”, updated the Baud Rate value from “33,400” to “38,400” in Table 40-
10 ”Maximum Time-out Period”.
Section 40.7.5.3 ”IrDA Demodulator”, added a paragraph on IRDA_FILTER programming criteria.
Section 40.7.8.16 ”LIN Frame Handling With the DMAC”, removed abundant “DMAC” acronym in the 1st
paragraph.
Section 40.8 ”Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface”:
- Table 40-17 ”Register Mapping”:
- added a row for LIN Baud Rate Register (offset 0x005C)
- updated offset values and added a new row for reserved registers (0x0060-0x00E0, 0x00EC-0x00FC)
- added Section 40.8.28 ”USART LIN Baud Rate Register”
- Section 40.8.22 ”USART FI DI RATIO Register”:
- US_FIDI register table: expanded FI_DI_RATIO bitfield to 16 bits
9356
rfo
8943
8508
8445/
8943
8445
8643
Doc. Rev
11063J
Comments Change
Request
Ref.