Datasheet

1084
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
TC:
Section 37.7 ”Timer Counter (TC) User Interface”:
- changed the order of register description sections to match Table 37-5 ”Register Mapping”
Section 37.7.2 ”TC Channel Mode Register: Capture Mode”:
- TCCLKS: added details for values 0 - 4 in the bitfield description table
Section 37.7.3 ”TC Channel Mode Register: Waveform Mode”:
- TCCLKS: added details for values 0 - 4 in the bitfield description table
- ENETRG: added a note on TIOA and TIOB controled by a selected external event
rfo
9107
8885/
9107
PWM:
Section 38.5.2 ”Power Management”, replaced the 2nd paragraph with a new content
8105
TWI:
Section 39.6.2 ”Power Management”, removed erroneous bullet “Enable the peripheral clock”.
Section 39.8 ”Master Mode”:
- Section 39.8.6.1 ”7-bit Slave Addressing”, replaced ‘N’ acronym with ‘NA’ in Table 39-6 ”Abbreviations”.
- Section 39.8.7.1 ”Data Transmit with the DMA”:
- added Steps 6 - 9
- Section 39.8.7.2 ”Data Receive with the DMA”:
- replaced the acronym ‘PDC’ with ‘DMA’ in the 1st paragraph
- added a paragraph on slave mode
- updated Step 2
- added Step 4 and Step 12
- Section 39.8.9 ”Read-write Flowcharts”, added missing “yes” and “no” in:
- Figure 39-18, "TWI Write Operation with Multiple Data Bytes with or without Internal Address"
- Figure 39-21, "TWI Read Operation with Multiple Data Bytes with or without Internal Address"
Section 39.10 ”Slave Mode”
- added Section 39.10.6 ”Using the DMA Controller” including subsections on data transmit and data
receive
rfo
rfo
8555/
8552/
rfo
8944/rfo
9055
Doc. Rev
11063J
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